remove unneeded version.h from lcd.c

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>

Use the GNU 'date' command to auto-generate a new U-Boot
timestamp on every compile.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Commit 6b59e03e
lcd: Let the board code show board-specific info

introduced some bugs which prevent U-Boot building
for lwmon board if CONFIG_LCD_INFO_BELOW_LOGO will
be defined in the board configuration.

Also "LCD enabled" building for TQM823L doesn't work
since this commit.

This patch fixes above-mentioned issues.

Signed-off-by: Anatolij Gustschin <agust@denx.de>

When using gdb, history files will often get generated.  So ignore them.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

This code contains some non-ascii characters in comment lines and code.
Most editors do not display those characters properly and editing those
files results always in diffs at these places which are usually not required
to be changed at all. This is error prone.

So, remove those weird characters and replace them by normal C-style
equivalents for which the proper defines were already in the header.

Signed-off-by: Remy Bohmer <linux@bohmer.net>

The default DDR freq is 400MHz or 800M data rate,
the old settings is pure wrong for the default case.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Moved up the initialization of GD so C code like set_tlb() can use
gd->flags to determine if we've relocated or not in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

If the virtual address for CCSRBAR is the same after relocation but
the physical address is changing we'd end up having two TLB entries with
the same VA.  Instead we new us the new CCSRBAR virt address + 4k as a
temp virt address to access the old CCSRBAR to relocate it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

The BR_PHYS_ADDR macro is useful on all machines that have local bus
which is pretty much all 83xx/85xx/86xx chips.

Additionally most 85xx & 86xx will need it if they want to support
36-bit physical addresses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

Add define used to determine if PCI1 interface is in PCI or PCIX mode.

Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

The current code will cause the creation of a 4GB window
starting at 0 if we have more than 4GB of RAM installed,
which overlaps with PCI_MEM space and causes pci_bus_to_phys()
to return erroneous information. Limit the size to 4GB - 1;
which causes the code to create one 2GB and one 1GB window
instead.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Removed while(1) hang if memctl_intlv_ctl is set wrong.
Remove embedded tabs from strings.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

since commit be0bd823
tlb entry for socrates DDR SDRAM will be reconfigured
by setup_ddr_tlbs() from initdram() causing an
inconsistency with previously configured DDR SDRAM tlb
entry from tlb_table:

socrates>l2cam 7 9
IDX  PID      EPN  SIZE V TS           RPN U0-U3 WIMGE UUUSSS
  7 : 00 00000000 256MB V  0 -> 0_00000000  0000 -I-G- ---RWX
  8 : 00 00000000 256MB V  0 -> 0_00000000  0000 ----- ---RWX
  9 : 00 10000000 256MB V  0 -> 0_10000000  0000 ----- ---RWX

This patch makes the presence of the DDR SDRAM tlb entry in
the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this
inconsistency.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>

All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>

we need TLB entry for DDR at !SPD case.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

This patch fix the problem that only the [NB_DATAFLASH_AREA - 1] dataflash
partition can be defined to use the area to the end of dataflash size.
Now it is possible to have only one dataflash partition from 0 to the end
of of dataflash size.

Signed-off-by: Ilko Iliev <iliev@ronetix.at>

This patch fix some coding style violations.

Signed-off-by: Ilko Iliev <iliev@ronetix.at>

Without this patch "saveenv" crashes when MTD partitions are enabled (e.g.
for use in UBI) via CONFIG_MTD_PARTITIONS.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>

I made some updates to the code that didn't make it into the
README - fix this

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>

Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.

Signed-off-by: Jon Loeliger <jdl@freescale.com>

Introducing 64-bit (36-bit) support for the MPC8641HPCN
failed to accomodate the other two 86xx boards.
Introduce definitions for CONFIG_SYS_CCSRBAR_PHYS_{LOW,HIGH}
CONFIG_SYS_CCSR_DEFAULT_DBAT{U,L} and CONFIG_SYS_CCSR_DEFAULT_IBAT{U,L}
with nominal 32-bit values.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>

Remove USB obsolete commmand

Signed-off-by: Michael Trimarchi <trimarchi@gandalf.sssup.it>
Signed-off-by: Remy Böhmer <linux@bohmer.net>

USB Code style patch

Signed-off-by: Michael Trimarchi <trimarchi@gandalf.sssup.it>
Signed-off-by: Remy Böhmer <linux@bohmer.net>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Remy Böhmer <linux@bohmer.net>

This caused the operation to be needlessly repeated if there were
no bad blocks and no errors.

Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

This BSP should be outside u-boot source tree.
The second reason is that xilinx ppc405 was moved to generic platform.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Stefan Roese <sr@denx.de>