Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.

Added this functionality on board_late_init as it's not
needed for normal initializtion part.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM012:
- 1GB DDR3
- 64MiB Numonyx NOR flash
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Stefan Roese <sr@denx.de>

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM013:
- 1GB DDR3
- 128 Mb Quad-SPI Flash(dual parallel)
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM010:
- 1Gb DDR3
- 1Mb SST SPI flash
- 128 Mb Quad-SPI Flash
- 8 Mb SST SI flash
- Full size SD/MMC card cage
- 10/100/1000 Ethernet
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

MicroZed is a low-cost development board based on
the Xilinx Zynq-7000 All Programmable SoC.

APSOC:
- XC7Z010-1CLG400C
Memory:
- 1 GB of DDR3 SDRAM
- 128Mb of QSPI flash(S25FL128SAGBHI200)
- Micro SD card interface
Communication:
- 10/100/1000 Ethernet
- USB 2.0
- USB-UART
User I/O:
- 100 User I/O (50 per connector)
- Configurable as up to 48 LVDS pairs or 100 single-ended I/O
Misc:
- Xilinx PC4 JTAG configuration port
- PS JTAG pins accessible via Pmod
- 33.33 MHz oscillator
- User LED and push switch

For more info - http://zedboard.org/product/microzed



Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Adds configurations for Catalyst 24WC08 EEPROM, which
is present on the zynq boards.

Enable EEPROM support for zc70x boards.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Defined TEXT_BASE for u-boot starts from 0x4000000
w.r.t zynq memory-map.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

CONFIG_SYS_SDRAM_SIZE is specific to a board hence moved
to specific pre-config board files.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Zed is a complete development board based on the
Xilinx Zynq-7000 All Programmable SoC.

APSOC:
- XC7Z020-CLG484-1
Memory:
- 512 MB DDR3
- 256 Mb Quad-SPI Flash(
- Full size SD/MMC card cage
Connectivity:
- 10/100/1000 Ethernet
- USB OTG (Device/Host/OTG)
- USB-UART
Expansion:
- FMC (Low Pin Count)
- Pmod. headers (2x6)
Video/Display:
- HDMI output (1080p60 + audio)
- VGA connector
- 128 x 32 OLED
- User LEDs (9)
User inputs:
- Slide switches (8)
- Push button switches (7)
Audio:
- 24-bit stereo audio CODEC
- Stereo line in/out
- Headphone
- Microphone input
Analog:
- Xilinx XADC header
- Supports 4 analog inputs
- 2 Differential / 4 Single-ended
Debug:
- On-board USB JTAG programming port
- ARM Debug Access Port (DAP)

For more info - http://zedboard.org/product/zedboard



Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

The Zynq-7000 APSOC zc702 and zc706 enabled complte embedded
processing includes ASIC and FPGA design.

ZC702-:

APSOC:
- XC7Z020-CLG484-1
Memory:
- DDR3 Component Memory 1GB
- 16MB Quad SPI Flash
- IIC - 1 KB EEPROM
Connectivity:
- Gigabit Ethernet GMII, RGMII and SGMII.
- USB OTG - Host USB
- IIC Bus Headers/HUB
- 1 CAN with Wake on CAN
- USB-UART
Video/Display:
- HDMI Video OUT
- 8X LEDs
Control & I/O:
- 3 User Push Buttons
- 2 User Switches
- 8 User LEDs

For more info on zc702 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm

ZC706-:

APSOC:
- XC7Z045 FFG900 -2 AP SoC
Memory:
- DDR3 Component Memory 1GB (PS)
- DDR3 SODIM Memory 1GB (PL)
- 2X16MB Quad SPI Flash (dual parallel)
- IIC - 1 KB EEPROM
Connectivity:
- PCIe Gen2x4
- SFP+ and SMA Pairs
- GigE RGMII Ethernet (PS)
- USB OTG 1 (PS) - Host USB
- IIC Bus Headers/HUB (PS)
- 1 CAN with Wake on CAN (PS)
- USB-UART
Video/Display:
- HDMI 8 color RGB 4.4.4 1080P-60 OUT
- HDMI IN 8 color RGB 4.4.4
Control & I/O:
- 2 User Push Buttons/Dip Switch, 2 User LEDs
- IIC access to GPIO
- SDIO (SD Card slot)
- 3 User Push Buttons, 2 User Switches, 8 User LEDs

For more info on zc706 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm



Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Information on zynq u-boot about
- zynq boards
- mainline status
- TODO

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

zynq.h -> zynq-common.h, zynq-common is Common
configuration options for all Zynq boards.

zynq.h is no longer exists hense removed from boards.cfg

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Zynq ethernet controller support two GEM's like
CONFIG_ZYNQ_GEM0 and CONFIG_ZYNQ_GEM1 enabled
both so-that the respective board will define
these macros based on their usage.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
enabled both so-that the respective board will define
these macros based on their usage.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

- Enable cache command
- Turn-off L2 cache
- Turn-on D-cache

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Cleanups mostly on:
- Add comments
- Re-order configs
- Remove #define CONFIG_ZYNQ_SDHCI

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Cleanup on memory configuration options:
- Add comment
- Re-order configs

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Cleanup on miscellaneous configurable options:
- Rename SYS_PROMPT as "zynq-uboot"
- Add comment
- Re-order configs

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

This enabled Boot FreeBSD/vxWorks from an ELF image support

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Enabled fit_format_{error,warning}()

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

The vexpress_aemv8a is the first aarch64 board in U-Boot.
As it was introduced, it gets built when "MAKEALL -a arm"
is invoked, and fails as this command is run with a 32-bit,
not 64-bit, toolchain as the cross-compiler.

Introduce 'aarch64' as a valid 'MAKEALL -a' argument, treated
as 'arm' for all other intents, and change the architecture
of the vexpress_aemv8a entry in boards.cfg from 'arm' to
'aarch64'.

The toolchain sets __aarch64__ for both LE and BE.  In the case of
posix_types.h we cannot reliably use config.h as that will lead to
problems.  In the case of byteorder.h it's clearer to check the EB flag
being set in either case instead.

Cc: David Feng <fenghua@phytium.com.cn>
Signed-off-by: Tom Rini <trini@ti.com>

Amended by Albert ARIBAUD <albert.u.boot@aribaud.net> to
actually remove the config.h include from the posix_types.h
files, with permission from Tom Rini.

Signed-off-by: David Feng <fenghua@phytium.com.cn>

Signed-off-by: David Feng <fenghua@phytium.com.cn>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>

Signed-off-by: David Feng <fenghua@phytium.com.cn>

Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: David Feng <fenghua@phytium.com.cn>

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>

While performing relocations on u-boot.bin should be good enough for
booting on real hardware, some simulators insist on booting an ELF file
(and yet don't perform ELF relocations), so convert the relocated
binary back into an ELF file.  This can go away in the future if we
change relocate-rela to operate directly on the ELF file, or if and
when we stop caring about a simulator with this restriction.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>

ARM64 uses the newer RELA-style relocations rather than the older REL.
RELA relocations have an addend in the relocation struct, rather than
expecting the loader to read a value from the location to be updated.

While this is beneficial for ordinary program loading, it's problematic
for U-Boot because the location to be updated starts out with zero,
rather than a pre-relocation value.  Since we need to be able to run C
code before relocation, we need a tool to apply the relocations at
build time.

In theory this tool is applicable to other newer architectures (mainly
64-bit), but currently the only relocations it supports are for arm64,
and it assumes a 64-bit little-endian target.  If the latter limitation
is ever to be changed, we'll need a way to tell the tool what format
the image is in.  Eventually this may be replaced by a tool that uses
libelf or similar and operates directly on the ELF file.  I've written
some code for such an approach but libelf does not make it easy to poke
addresses by memory address (rather than by section), and I was
hesitant to write code to manually parse the program headers and do the
update outside of libelf (or to iterate over sections) -- especially
since it wouldn't get test coverage on things like binaries with
multiple PT_LOAD segments.  This should be good enough for now to let
the manual relocation stuff be removed from the arm64 patches.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>

Signed-off-by: David Feng <fenghua@phytium.com.cn>

Signed-off-by: David Feng <fenghua@phytium.com.cn>

Signed-off-by: David Feng <fenghua@phytium.com.cn>

Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is
not working on some boards, modifying the offset to read properly.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>

Following commit "arm: omap3: Enable clocks for peripherals only if they are
used" (f33b9bd3) it is now necessary to enable
clocks for GPIO banks explicitly. On cm_t35, GPIO bank 5 is necessary for
scf0403 lcd support.

Enable GPIO bank 5 clocks.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>

Commit f33b9bd3 breaks boards
which do not explicitly enable the gpio clocks. This causes
the twister spl to hang, since it uses the no longer enabled
gpio 55. Add CONFIG_OMAP3_GPIO_2 to unbrick the board.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Stefano Babic <sbabic@denx.de>

commit f9095aac793aa8917ab9b915c5d449e6dc8d3d30, "mtd: nand:
omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme"
removed CONFIG_SPL_NAND_SOFTECC from the tam3517 common config,
causing the spl nand boot to fail. Add it back, so derived
boards boot again.

Cc: Pekon Gupta <pekon@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Raphael Assenat <raph@8d.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Stefano Babic <sbabic@denx.de>

The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.

Signed-off-by: Tom Rini <trini@ti.com>

With the changes to make OOBFREE/ECCPOS configurable but default to
larger, we need to set these config options for the space savings they
provide.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>

Due to the i2c mux rework in u-boot we now have only to specify the
busnumber and not the whole mux configuration.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>