- Apr 04, 2011
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Kumar Gala authored
Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Mar 24, 2011
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York Sun authored
rcw_en bit is only available for DDR3 controllers. It is a reserved bit on DDR1 and DDR2 controllers. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Mar 05, 2011
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York Sun authored
The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Feb 11, 2011
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York Sun authored
When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Jan 25, 2011
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Kumar Gala authored
ctrl_regs.c: In function 'set_ddr_sdram_mode_2': ctrl_regs.c:690:6: warning: unused variable 'i' 'i' is only used by DDR3 code. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Jan 20, 2011
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York Sun authored
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Haiying Wang authored
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in case that the DDR SDRAM is initialized in the 2nd stage uboot and should not be intialized again in the final stage uboot. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Oct 20, 2010
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York Sun authored
When DDR controller interleaving is eabled and less than all bank (chip-select) interleaving is seletected, the unused chip-select should be disabled. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Aug 31, 2010
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York Sun authored
Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Jul 26, 2010
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York Sun authored
Changes for P2020DS DDR applies to other 8xxx platform Signed-off-by:
York Sun <yorksun@freescale.com>
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York Sun authored
Enabled registered DIMMs using data from SPD. RDIMMs have registers which need to be configured before using. The register configuration words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software should read those RCWs and put into DDR controller before initialization. Signed-off-by:
York Sun <yorksun@freescale.com>
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York Sun authored
For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by:
York Sun <yorksun@freescale.com>
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York Sun authored
Previous code presumes each DIMM has up to two rank (chip select). Newer DDR controller supports up to four chip select on one DIMM. Signed-off-by:
York Sun <yorksun@freescale.com>
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York Sun authored
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual rank with 512MB each rank. Also check dimm size and rank size for memory controller interleaving Signed-off-by:
York Sun <yorksun@freescale.com>
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- Apr 27, 2010
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Dave Liu authored
Add an extra cycle turnaround time to read->write to ensure stability at high DDR frequencies. Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Apr 21, 2010
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Stefan Roese authored
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by:
Stefan Roese <sr@denx.de> Acked-by:
Wolfgang Denk <wd@denx.de> Acked-by:
Detlev Zundel <dzu@denx.de> Acked-by:
Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
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- Apr 13, 2010
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Peter Tyser authored
Signed-off-by:
Peter Tyser <ptyser@xes-inc.com>
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- Apr 07, 2010
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Dave Liu authored
Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by:
Dave Liu <daveliu@freescale.com>
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- Jan 05, 2010
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Dave Liu authored
In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Dave Liu authored
Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Dave Liu authored
add the override for write leveling sampling and start time according to specific board. Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Dave Liu authored
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Oct 03, 2009
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Kumar Gala authored
* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong * Fix the format string to match size in a debug print Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Sep 16, 2009
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Kumar Gala authored
* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong * Fix the format string to match size in a debug print Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Sep 08, 2009
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Kumar Gala authored
The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Jun 12, 2009
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Kumar Gala authored
The ddr code computes most things as 64-bit quantities and had some places in the middle that it was using phy_addr_t and phys_size_t. Instead we use unsigned long long through out and only at the last stage of setting the LAWs and reporting the amount of memory to the board code do we truncate down to what we can cover via phys_size_t. This has the added benefit that the DDR controller itself is always setup the same way regardless of how much memory we have. Its only the LAW setup that limits what is visible to the system. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Mar 30, 2009
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Dave Liu authored
- support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
Travis Wheatley <travis.wheatley@freescale.com>
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Dave Liu authored
1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case. Reported-by:
Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by:
Dave Liu <daveliu@freescale.com>
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- Jan 23, 2009
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Dave Liu authored
Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by:
Dave Liu <daveliu@freescale.com> Acked-by:
Andy Fleming <afleming@freescale.com>
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Dave Liu authored
- The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by:
Dave Liu <daveliu@freescale.com> Acked-by:
Andy Fleming <afleming@freescale.com>
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Dave Liu authored
According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by:
Dave Liu <daveliu@freescale.com>
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- Oct 18, 2008
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Haiying Wang authored
Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Haiying Wang authored
Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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- Sep 06, 2008
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Kumar Gala authored
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs': ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function ctrl_regs.c:523: note: 'caslat' was declared here Add a warning in DDR1 case if cas_latency isn't a value we know about. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Acked-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- Aug 27, 2008
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Kumar Gala authored
The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by:
James Yang <James.Yang@freescale.com> Signed-off-by:
Jon Loeliger <jdl@freescale.com> Signed-off-by:
Becky Bruce <becky.bruce@freescale.com> Signed-off-by:
Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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