The path the goto takes doesn't ever write to the integer stack
variables soc and current, so gcc's compilation rightfully aborts due to
-Wmaybe-uninitialized.

Set them to 0 in this branch to make the compilation pass.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>

It is 2025 my dudes.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>

Heinrich Schuchardt authored 2 years ago and Nicolas Frattaroli committed 1 month ago

The declarations in the header and in the implementation must match.

Reported-by: Sergei Antonov <saproj@gmail.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

'bl2_to_bl31_params->bl32_ep_info' is Null and '&bl2_to_bl31_params->bl32_ep_info->pc'
is 0x8 when bl32 is absent. That means the pc value is determined by u-boot-spl.bin.
The 0x8 offset of u-boot-spl.bin is the value of '_TEXT_BASE', i.e. CONFIG_SPL_TEXT_BASE.

So far, only rk3576 without bl32 would trigger this issue as DRAM base is 0x40000000.

Let's init bl32_{ep,image}_info even bl32 is absent.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic928301baee1c7941f0befd7a89aa74dcbd88cb2

Some DM device is accessed at very late stage, such as RNG in
board_rng_seed(). We have to dryrun it early to setup the available
DM device resource for the late access.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I5bda8553b1b017567877c48a3c00dd39125ef09f

Build a smaller uboot.img, the size is 1MB.

Change-Id: I417ec1d435d8ef7dae75586650533f80f273bbac
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>

rockusb vs r/w no need depends on vendor storage. It already
supports many other paths to store secure data.

Change-Id: I4b47227fb00978082c57b1af4c96c63d12c51ed7
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
Change-Id: I5aa1f2249b1197d65ee3d9a7ff23c31724462da1

Change-Id: Ibee79c0860f4c80b080a2cc50c35624d58cb1d37
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>

developer may set security level to 2, then set security
level to 0, we should check security level in the case.

Change-Id: I831e525683646fc0ed0ac1aa8b1e236a5a0264d7
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>

The v1pll may be disabled in kernel and the gpll is always on.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I06dc90709563f7f5e7bc3b6837fc430ae27c1b25

Build command: ./make.sh rk3502

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Iff8a2c97d4456e755ca5f84790994711bc009f40

Already support avoid initializing mmc multiple times.

Change-Id: I06a007011fc0386ebecc95ee726420f811ba7d24
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

Change-Id: Ia827c85c4c3bf2d2dc4bf0da561a543a63beff95
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

Already support avoid initializing mmc multiple times.

Change-Id: I21251b81822d68ac240528c1d8cf4825cbdfa8d2
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

Change-Id: I3fc9de6c700a65d3b5dd56915b83c829810445a9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

Change-Id: Ibeaae28330a1dc89227848deb377c2d3377dad7b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

Delay 3 seconds to make sure power supply is steady.

Change-Id: Ieefae68fa52f23efb7315221d425b31650ae0883
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

Change-Id: I865dd92c34d439b0a1e0d27a0b67410dfa2ef611
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

For rk3568, rsa4096 flag and secureboot flag should be
burned together because of ecc enable.

Change-Id: I75e6171d37abc589f433462d0f055df01e604799
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

1. If burn both flags(0x30ff) into OTP_SECURE_BOOT_ENABLE_ADDR,
0xff will be burned first. If power down happens when burn rsa4096 flag
(0xff is already burned), the device becomes bricked.

2. So, fix all OTP_SECURE_BOOT_ENABLE_SIZE from 2 bytes to 1 byte,
only allow to burn 1 byte to open secureboot. Add OTP_RSA4096_ENABLE_ADDR/SIZE
definition used for burn rsa4096 flag.

Change-Id: Ifc9767242bc86fd0cf69ff107b4f557bc3a4fdcd
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

Change-Id: I4a550b94b6128d9131762bfece447d4da9a93099
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

Change-Id: Idcea7eb5425dbf875376ad98851ea8b94b4be3d9
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

Change-Id: I21632dd799df231f03b9aee9c91be44d798b468a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

Change-Id: Icb97fe90b50ebf44eae673b6f3e6979d65a59079
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

Change-Id: If1044efe918f854085c019adad803687e01449e9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

Change-Id: Ib990fc028978f9b549c5d12fb3fb1c406858abc8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

1. Delaying the initialization of phy can solve the problem of
UFS initialization getting stuck when phy is not powered on.
2. Config linkup timeout to 150ms.
3. Config NOP_OUT_TIMEOUT to 1500ms.
4. Add retry for dev init.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I7b3dc1d3245e27626ab81f0807146b7e05507f27

Change-Id: I8ac6c59fcf9035ea86c6601d46731d6c24c7ae8a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

Change-Id: I4d4e2239d237307fc722f81e359283703f51cc50
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

Change-Id: I4416b004d315f2f5689312b1eb53e36fce7f6bbf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

In order to enable dual NOR flash users to experience double the
capacity and avoid frequent switching between two NOR flash devices,
the two NOR flash devices are virtualized into one device, which
I name it auto_merge tech.

Change-Id: I5edd7cde0481b1de6a35fce7ac67068889ff5ffe
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

SATA/USB/GMAC default Qos is 0x0, it is too low for peripheral, set to 0x404
to be same as other peripherals.

Signed-off-by: CanYang He <hcy@rock-chips.com>
Change-Id: Ib16efb77c91f3a819eba1c1e18f66d53a8aab427

set DMAC0 to priority 0x404 to keep the same with DMAC1/2
which had been set 0x404 by default.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I752c03a0b7d1026fe852965b13f65b789e14ab27

Change-Id: I88edf35ccac836e8445d298c3b08420c47d10987
Signed-off-by: William Wu <william.wu@rock-chips.com>

This patch reset usb controller and resume usb phy to
normal mode, and also set the usb utmi bvalid to high
from grf for usb download mode.

Change-Id: I98c3e44183b2f5b4c11a62246c6dc9530b109963
Signed-off-by: William Wu <william.wu@rock-chips.com>

Change-Id: I760c800876faafc2ea4947a4d5c7884708c0e513
Signed-off-by: William Wu <william.wu@rock-chips.com>

Change-Id: Ie22d23b5a69a517166a60e127996f408c60215cf
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

Change-Id: If503220306d90f3b8660c93914d53568eeb7fdb4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

Avoid affecting spiflash startup.

Change-Id: I9b1ec00fabd5e7a5f57eb1eacd4d79658121cf45
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>