- Dec 24, 2024
-
-
This is a defconfig for all MediaTek Chromebooks, running on ArchLinux, Debian, ChromiumOS or PostmarketOS. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Checking of_machine_is_compatible() for each machine is just an open coded version of of_machine_compatible_match(): add a new allowlist array of compatibles and iteratively check those by calling said function. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Calling cmdq packet builders with an unsupported event number, or without left/right operands (in the case of logic commands) means that the caller (another driver) wants to perform an unsupported operation, so this means that the caller must be fixed instead. Anyway, such checks are here for safety and, unless any driver bug or any kind of misconfiguration is present, will always be false so add a very unlikely hint for those. Knowing that CPUs' branch predictors (and compilers, anyway) are indeed smart about these cases, this is done mainly for human readability purposes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Use the kernel provided dev_err_ptr_probe() and dev_err_probe() in all probe error return paths where possible. While at it, also beautify the device link error message. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
This replaces all occurrences of (1 << x) with BIT(x). No functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Describe the PMIC-integrated Auxiliary Analog to Digital Converter subdevice node. Full description is available in the mediatek,mt6359-auxadc.yaml binding relative to that hardware. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Enable the Audio Front End (AFE) and add support for the PMIC integrated sound card, exposed at the onboard 4-pole 3.5mm jack. Also add a comment note signaling that the support for HDMI and DisplayPort audio is missing; this is because: - The HDMI TX controller is not yet enabled and, at the time of writing, there's no driver yet; - The DisplayPort is not yet enabled, but the driver is available upstream and will be added at a later time. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Load the MT8195 SCP firmware, as it is compatible with MT8395, and also add the SCP_VREQ_VAO pin to set it as input as required: this enables both vcodec with stateless decoding and stateful encoding with the same codecs supported by the MT8195 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Add aliases for MMC0 and MMC1 to get consistent device numbers for the eMMC and for the MicroSD card. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Enable the UFS PHY and UFS controller with its required power supplies to enable using the UFS card on this board. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Add a node for the Universal Flash Storage controller and keep it disabled by default. While at it, also change the UFS PHY node to use the right clocks for unipro and mp to improve reliability on platforms that don't enable, or that disable, UFS in the bootloader before booting the kernel. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
-
Add support for a DSI display connected to the DSI0 output. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
The display IPs in MT8195 are flexible and those support being interconnected with different instances of DDP IPs and/or with different DDP IPs, forming a full Display Data Path that ends with an actual display output, which is board-specific. Add a common graph in the main mt8195.dtsi DT, shared between all of the currently supported boards (including IoT and EVK) to avoid cluttering device-specific DTs, and add the relevant board-specific graph in mt8195-cherry, shared between all of the currently supported MT8195 Chromebooks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Add a node for the Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) and subnodes for the DVFSRC regulators, supplying power to CPU Cores and SCP, and External Memory Interface (EMI) interconnect. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
When probing multi-core SCP, this driver is parsing all sub-nodes of the scp-cluster node, but one of those could be not an actual SCP core and that would make the entire SCP cluster to fail probing for no good reason. To fix that, in scp_add_multi_core() treat a subnode as a SCP Core by parsing only available subnodes having compatible "mediatek,scp-core". Fixes: 1fdbf0cd ("remoteproc: mediatek: Probe SCP cluster on multi-core SCP") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
The System Companion Processor block in MT8195 has 768KB of L2TCM shared with the two SCP cores. Fix the sram iospace to be 768KB instead of 1MB long. Fixes: 867477a5 ("arm64: dts: mt8195: Add scp node") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
The drivers and bindings acquired support for specifying audio hardware and links in device tree: describe and link the sound related HW of this machine. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Move the simple component check to a new mtk_ddp_is_simple_comp() internal helper to reduce code duplication. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Add a new mtk_ddp_comp_destroy() function and call it in the teardown path of mtk_drm_drv to make sure that we unmap the iospace of the simple DDP components. While at it, also fix iounmapping on mtk_ddp_comp_init() error path. Fixes: ff139560 ("drm/mediatek: Move mtk_ddp_comp_init() from sub driver to DRM driver") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
As per Stephen Boyd's request, add the drivers/clk/mediatek folder to ARM/Mediatek SoC support. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
-
-
Add audio support for it6505 1. Bridge to hdmi-codec to support audio feature. At the same time, the function of automatically detecting audio is removed. 2. It is observed that some DP-to-HDMI dongles will get into bad states if sending InfoFrame without audio data. Defer to enable it6505's audio feature when PCM triggers START or RESUME. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
-
Use SND_SOC_DAPM_LINE instead of SND_SOC_DAPM_OUTPUT to trigger DAPM events to hdmi-codec when userspace control the DPAM pin. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
-
If the speaker and hdmi are connect to the same port of I2S, when try to switch to speaker playback, we will find that hdmi is always turned on automatically. The connection as follows: ==> hdmi-codec ==> it6505(HDMI output) DL1(FE) ==> I2S3(BE) ==> rt1015p(SPEAKER output) So in order to separately control their power on/off, we have added a dapm widget to notify each output. Also the machine driver need add a _PIN_SWITCH() on the output of the device that will cause DAPM to keep the device powered down when not in use. The purpose of adding .trigger callback here is to enable hdmi-codec to notify the dp output driver to power on or off device. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
-
The driver for MediaTek gen3 PCIe hosts de-asserts all reset signals at the same time using a single register write operation. Delay the de-assertion of the #PERST signal by 100ms as required by PCIe CEM clause 2.2, some PCIe devices fail to come up otherwise. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-
In order to enhance human readability, separating the optional CMDQ mailbox initialization from the rest of the CRTC creation machinery, move it to a new mtk_drm_cmdq_init() function. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Since this driver was migrated to use the MediaTek CMDQ helpers, it's not anymore necessary to exclude CMDQ related code with preprocessor if branches, as CMDQ is optional and the helpers are providing the necessary inline functions to manage the case in which CONFIG_MTK_CMDQ is not set. Clean up all instances of `#if IS_REACHABLE(CONFIG_MTK_CMDQ)` from all drivers in drm/mediatek. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Instead of stack allocating the cmdq_client and cmdq_handle structures switch them to pointers, allowing us to migrate this driver to use the common functions provided by mtk-cmdq-helper. In order to do this, it was also necessary to add a `priv` pointer to struct cmdq_client, as that's used to pass (in this case) a mtk_crtc handle to the ddp_cmdq_cb() mailbox RX callback function. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Nícolas F. R. A. Prado authored
Add the CLK_VDEC_ACTIVE clock to the vdec clock driver. This clock is enabled by the VPU once it starts decoding. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-
The MediaTek MSDC controller has an internal divider for the input (source) clock, but that may not be enough: as there's no multiplier it is impossible to achieve certain clock rates depending on the source clock rate. This is especially seen with the SDR104 mode, where a clock source typically of 200MHz or 400MHz will make us able to achieve 200MHz (depending on the SoC's MSDCPLL, this will be more likely ~199MHz) instead of the optimal 208MHz. In order to solve this issue and achieve an accurate clock rate for all modes, call clk_set_rate() on the source clock, so that the clock framework will either change the PLL's rate or, more likely, will switch the clock parent to the "best" one. As an example, on MT8195, an accurate frequency will be achieved by reparenting of the source clock from msdcpll div2 to univpll div6-div2, giving out exactly 208000000Hz. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
-
After 3 retries, ignore sleep ctrl not ready. This allows PM suspend of the SoC with a power consumption that is possibly slightly higher than expected. Still better than no suspend at all. The proper fix for this is to reset the LARB if SLP_PROT_RDY is never triggered. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
While it is possible to run the standard UHS104/SDR104 at 200MHz, the correct clock rate for this specification is 208MHz, so, 8MHz more. This ensures that the maximum possible performance can be achieved, as theoretically +8MHz means a +4MB/s throughput. Fixes: 07984e82 ("arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
In mtk_pcie_suspend_noirq() and mtk_pcie_resume_noirq() we are, respectively, disabling and enabling generation of interrupts and then saving and restoring the enabled interrupts register: since we're using noirq PM callbacks, that can be safely done without holding any spin lock. That was noticed because of, and solves, the following issue: <4>[ 74.185982] ======================================================== <4>[ 74.192629] WARNING: possible irq lock inversion dependency detected <4>[ 74.199276] 6.3.0-next-20230428+ #51 Tainted: G W <4>[ 74.205664] -------------------------------------------------------- <4>[ 74.212309] systemd-sleep/809 just changed the state of lock: <4>[ 74.218347] ffff65a5c34c65a0 (&pcie->irq_lock){+...}-{2:2}, at: mtk_pcie_resume+0x50/0xa8 <4>[ 74.226870] but this lock was taken by another, HARDIRQ-safe lock in the past: <4>[ 74.234389] (&irq_desc_lock_class){-.-.}-{2:2} <4>[ 74.234409] <4>[ 74.234409] <4>[ 74.234409] and interrupts could create inverse lock ordering between them. <4>[ 74.234409] <4>[ 74.251704] <4>[ 74.251704] other info that might help us debug this: <4>[ 74.258785] Possible interrupt unsafe locking scenario: <4>[ 74.258785] <4>[ 74.266126] CPU0 CPU1 <4>[ 74.270942] ---- ---- <4>[ 74.275758] lock(&pcie->irq_lock); <4>[ 74.279627] local_irq_disable(); <4>[ 74.285836] lock(&irq_desc_lock_class); <4>[ 74.292667] lock(&pcie->irq_lock); <4>[ 74.299061] <Interrupt> <4>[ 74.301960] lock(&irq_desc_lock_class); <4>[ 74.306438] <4>[ 74.306438] *** DEADLOCK *** Fixes: d537dc12 ("PCI: mediatek-gen3: Add system PM support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
In order to reduce decoder latency, enable VP9 inner racing mode. Send lat trans buffer information to core when trigger lat to work, need not to wait until lat decode done. Signed-off-by: mingjia zhang <mingjia.zhang@mediatek.com> [Angelo: Ported to next-20230804] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Some PMICs have a separated WLED string output: add a property `mediatek,is-wled` to indicate which LED string is a WLED. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
Communication with the AudioDSP is impossible if it has no power. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
On Tomato rev1 the PCIe0 controller is used for NVMe storage. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-