• Roger Quadros's avatar
    ARM: dts: dra7: Add bus_dma_limit for L3 bus · cfb5d65f
    Roger Quadros authored
    The L3 interconnect's memory map is from 0x0 to
    0xffffffff. Out of this, System memory (SDRAM) can be
    accessed from 0x80000000 to 0xffffffff (2GB)
    DRA7 does support 4GB of SDRAM but upper 2GB can only be
    accessed by the MPU subsystem.
    Add the dma-ranges property to reflect the physical address limit
    of the L3 bus.
    Issues ere observed only with SATA on DRA7-EVM with 4GB RAM
    and CONFIG_ARM_LPAE enabled. This is because the controller
    supports 64-bit DMA and its driver sets the dma_mask to 64-bit
    thus resulting in DMA accesses beyond L3 limit of 2G.
    Setting the correct bus_dma_limit fixes the issue.
    Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
    Cc: stable@kernel.org
    Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
dra7.dtsi 24.9 KB