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Commit d0055777 authored by Sebastian Reichel's avatar Sebastian Reichel Committed by Sebastian Reichel
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arm64: dts: imx95: add DT for DART-MX95 Development Kit


Add board DT based on the vendor kernel, but adapted for the
close-to-upstream kernel tree.

Co-developed-by: default avatarLeonid Segal <leonid.s@variscite.com>
Co-developed-by: default avatarFrancescoFerraro <francesco.f@variscite.com>
Signed-off-by: default avatarLeonid Segal <leonid.s@variscite.com>
Signed-off-by: default avatarFrancescoFerraro <francesco.f@variscite.com>
Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
parent ca0a2acf
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Pipeline #120226 passed
...@@ -269,6 +269,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb ...@@ -269,6 +269,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-variscape-dt8mcustomboard.dtb
imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo
......
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 NXP
* Copyright 2024 Variscite Ltd.
*/
#include "imx95.dtsi"
/ {
model = "Variscite DART-MX95 SOM";
compatible = "variscite,dart-mx95", "fsl,imx95";
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "+V1.8_SW";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "+V3.3_SW";
};
reg_audio: regulator-audio-vdd {
compatible = "regulator-fixed";
regulator-name = "wm8904_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_enet0_phy: regulator-enet0-phy {
compatible = "regulator-fixed";
regulator-name = "enet0-phy";
gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
status = "okay";
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux_cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x3c000000>;
alloc-ranges = <0 0x80000000 0 0x7F000000>;
linux,cma-default;
};
vpu_boot: vpu_boot@a0000000 {
reg = <0 0xa0000000 0 0x100000>;
no-map;
};
vdev0vring0: vdev0vring0@88000000 {
reg = <0 0x88000000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@88008000 {
reg = <0 0x88008000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@88010000 {
reg = <0 0x88010000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@88018000 {
reg = <0 0x88018000 0 0x8000>;
no-map;
};
rsc_table: rsc-table@88220000 {
reg = <0 0x88220000 0 0x1000>;
no-map;
};
vdevbuffer: vdevbuffer@88020000 {
compatible = "shared-dma-pool";
reg = <0 0x88020000 0 0x100000>;
no-map;
};
};
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
simple-audio-card,mclk-fs = <256>;
dailink_master: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio2 27 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
status = "okay";
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
#if 0
&enetc_port0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
status = "okay";
};
#endif
&lpi2c8 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default","gpio","sleep";
pinctrl-0 = <&pinctrl_lpi2c8>;
pinctrl-1 = <&pinctrl_lpi2c8_gpio>;
pinctrl-2 = <&pinctrl_lpi2c8_gpio>;
scl-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
status = "okay";
wm8904: codec@1a {
compatible = "wlf,wm8904";
#sound-dai-cells = <0>;
reg = <0x1a>;
clocks = <&scmi_clk IMX95_CLK_SAI3>;
clock-names = "mclk";
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
num-drc-cfgs = <5>;
drc-cfg-names = "default", "peaklimiter", "tradition", "soft", "music";
drc-cfg-regs =
/* coded default: KNEE_IP = KNEE_OP = 0, HI_COMP = LO_COMP = 1 */
<0x01af 0x3248 0x0000 0x0000>,
/* coded default: KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 */
<0x04af 0x324b 0x0010 0x0408>,
/* coded default: KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 */
<0x04af 0x324b 0x0028 0x0704>,
/* coded default: KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 */
<0x04af 0x324b 0x0018 0x078c>,
/* coded default: KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 */
<0x04af 0x324b 0x0010 0x050e>;
gpio-cfg = <
0x0018 /* GPIO1 => DMIC_CLK */
0xffff /* GPIO2 => don't touch */
0xffff /* GPIO3 => don't touch */
0xffff /* GPIO4 => don't touch */
>;
status = "okay";
};
};
&lpuart1 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
#if 0
&netc_emdio {
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
eee-broken-1000t;
mxl-8611x,led0_cfg = <(
MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON |
MXL8611X_LEDX_CFG_TRAFFIC_ACT_BLINK_IND
)>;
mxl-8611x,led1_cfg = <(
MXL8611X_LEDX_CFG_LINK_UP_10MB_ON |
MXL8611X_LEDX_CFG_LINK_UP_100MB_ON |
MXL8611X_LEDX_CFG_LINK_UP_1GB_ON
)>;
};
};
#endif
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&scmi_iomuxc {
pinctrl_enetc0: enetc0grp {
fsl,pins = <
IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e
IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x57e
IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e
IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e
IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e
IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e
IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x5fe
IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x5fe
IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e
IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e
IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e
IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e
>;
};
pinctrl_lpi2c8: lpi2c8grp {
fsl,pins = <
IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x40000b9e
IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x40000b9e
>;
};
pinctrl_lpi2c8_gpio: lpi2c8grp-gpio {
fsl,pins = <
IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e
IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e
IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e
IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc3_gpio: usdhc3gpiogrp {
fsl,pins = <
IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x31e
IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x31e
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x1582
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x1382
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
};
&usdhc1 {
pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-3 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
/* WiFi */
&usdhc3 {
pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
pinctrl-3 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
mmc-pwrseq = <&usdhc3_pwrseq>;
bus-width = <4>;
non-removable;
wakeup-source;
keep-power-in-suspend;
status = "okay";
};
&wdog3 {
status = "okay";
};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 NXP
* Copyright 2024 Variscite Ltd.
*/
/dts-v1/;
#include <dt-bindings/clock/nxp,imx95-clock.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/usb/pd.h>
#include "imx95-variscape-dart-mx95.dtsi"
/ {
model = "Variscite DART-MX95 on DT8MCustomBoard 3.x";
#if 0
aliases {
ethernet0 = &enetc_port0;
ethernet1 = &enetc_port1;
};
#endif
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&tpm4 3 1000000 0>;
status = "okay";
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
};
can0_osc: can0_osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
chosen {
stdout-path = &lpuart1;
};
clk_ov5640_fixed: clock {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
status = "okay";
heartbeat {
label = "Heartbeat";
gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
gpio-keys {
compatible = "gpio-keys";
status = "okay";
back {
label = "Back";
linux,code = <KEY_BACK>;
gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
wakeup-source;
};
up {
label = "Up";
linux,code = <KEY_UP>;
gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
wakeup-source;
};
home {
label = "Home";
linux,code = <KEY_HOME>;
gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
wakeup-source;
};
down {
label = "Down";
linux,code = <KEY_DOWN>;
gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
panel {
compatible = "sgd,gktw70sdae4se", "panel-lvds";
backlight = <&backlight>;
width-mm = <153>;
height-mm = <87>;
label = "gktw70sdae4se";
data-mapping = "jeida-24";
status = "okay";
panel-timing {
clock-frequency = <74250000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <40>;
vback-porch = <29>;
vfront-porch = <13>;
hsync-len = <48>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
};
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
reg_enet1_phy: regulator-enet1-phy {
compatible = "regulator-fixed";
regulator-name = "enet1-phy";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
status = "okay";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VDD_SD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <12000>;
enable-active-high;
};
};
&displaymix_irqsteer {
status = "okay";
};
&display_pixel_link {
status = "okay";
};
&dpu {
status = "okay";
};
#if 0
&enetc_port1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc1>;
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
status = "okay";
};
#endif
&gpio1 {
status = "okay";
};
&ldb0_phy {
status = "okay";
};
&ldb {
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&scmi_clk IMX95_CLK_LDBPLL_VCO>,
<&scmi_clk IMX95_CLK_LDBPLL>;
assigned-clock-rates = <4158000000>, <519750000>;
status = "okay";
channel@0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
reg = <0>;
port@1 {
reg = <1>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
status = "okay";
/* DS1337 RTC module */
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
status = "okay";
};
/* Capacitive touch controller */
ft5x06_ts: ft5x06_ts@38 {
compatible = "edt,edt-ft5206";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_captouch>;
reg = <0x38>;
reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
status = "okay";
};
#if 0
typec@3d {
compatible = "nxp,ptn5150";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
reg = <0x3d>;
int-gpios =<&gpio5 14 GPIO_ACTIVE_HIGH>;
irq-is-id-quirk;
status ="okay";
port {
typec_dr_sw: endpoint {
remote-endpoint = <&usb3_drd_sw>;
};
};
typec_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
};
};
};
};
#endif
};
&lpi2c8 {
pca6408_1: gpio@20 {
compatible = "nxp,pcal6408";
standard-regs-fallback;
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca6408>;
interrupt-parent = <&gpio5>;
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
};
pca6408_2: gpio@21 {
compatible = "nxp,pcal6408";
standard-regs-fallback;
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
&lpspi7 {
fsl,spi-num-chipselects = <3>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpspi7>;
pinctrl-1 = <&pinctrl_lpspi7>;
cs-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>,
<&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio5 4 GPIO_ACTIVE_LOW>;
status = "okay";
/* Resistive touch controller */
ads7846@0 {
compatible = "ti,ads7846";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_restouch>;
interrupt-parent = <&gpio2>;
interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <1500000>;
pendown-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <125>;
ti,x-max = /bits/ 16 <4008>;
ti,y-min = /bits/ 16 <282>;
ti,y-max = /bits/ 16 <3864>;
ti,x-plate-ohms = /bits/ 16 <180>;
ti,pressure-max = /bits/ 16 <255>;
ti,debounce-max = /bits/ 16 <10>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <1>;
ti,settle-delay-usec = /bits/ 16 <150>;
ti,keep-vref-on;
wakeup-source;
status = "okay";
};
can0: can@1 {
compatible = "microchip,mcp251xfd";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
interrupts-extended = <&gpio5 15 IRQ_TYPE_LEVEL_LOW>;
microchip,rx-int-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
clocks = <&can0_osc>;
spi-max-frequency = <12000000>;
status = "okay";
};
spidev0: spi@2 {
reg = <2>;
compatible = "lwn,bk4";
spi-max-frequency = <1000000>;
};
};
/* Header (J12.4, J12.6) */
&lpuart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
status = "okay";
};
#if 0
&netc_emdio {
phy-supply = <&reg_enet1_phy>;
status = "okay";
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
eee-broken-1000t;
reg = <1>;
};
};
#endif
&pcie0 {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
status = "okay";
};
&pixel_interleaver {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
channel@0 {
reg = <0>;
status = "okay";
};
};
&scmi_iomuxc {
pinctrl_can: cangrp {
fsl,pins = <
IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x31e
IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x31e
>;
};
pinctrl_captouch: captouchgrp {
fsl,pins = <
IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x31e
>;
};
pinctrl_enetc1: enetc1grp {
fsl,pins = <
IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x57e
IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e
IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e
IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e
IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e
IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e
IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x57e
IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e
IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e
IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e
IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e
IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e
>;
};
pinctrl_pwm_backlight: backlightgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO25__TPM4_CH3 0x51e
>;
};
pinctrl_gpio_leds: ledgrp {
fsl,pins = <
IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x31e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c3_gpio: lpi2c3grp-gpio {
fsl,pins = <
IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x31e
IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x31e
>;
};
pinctrl_lpspi7: lpspi7grp {
fsl,pins = <
IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe /* j16.4 ADS7846 */
IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x3fe /* j14.4 MCP2518FDT */
IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x3fe /* j25.2 spidev */
IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x3fe
IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x3fe
IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x3fe
>;
};
pinctrl_pca6408: pca6408grp {
fsl,pins = <
IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x31e
>;
};
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x31e
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e
IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};
&tpm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_backlight>;
status = "okay";
};
#if 0
&usb2 {
dr_mode = "host";
hnp-disable;
srp-disable;
adp-disable;
disable-over-current;
status = "okay";
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
role-switch-default-mode = "none";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
port {
usb3_drd_sw: endpoint {
remote-endpoint = <&typec_dr_sw>;
};
};
};
&usb3_phy {
status = "okay";
lane-swapp-disable-quirk;
port {
usb3_data_ss: endpoint {
remote-endpoint = <&typec_con_ss>;
};
};
};
#endif
&usdhc2 {
pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
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