Skip to content
Snippets Groups Projects
Commit cddd07cb authored by Sebastian Reichel's avatar Sebastian Reichel Committed by Sebastian Reichel
Browse files

usb: dwc3: add optional PHY interface clocks


On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
requires two extra clocks to be enabled. Without these extra clocks
hot-plugging USB devices is broken.

Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
parent 974456c4
No related branches found
No related tags found
2 merge requests!18[DRAFT v2] HDMIRX Support,!17Draft: HDMIRX support
......@@ -817,8 +817,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc)
if (ret)
goto disable_ref_clk;
ret = clk_prepare_enable(dwc->utmi_clk);
if (ret)
goto disable_susp_clk;
ret = clk_prepare_enable(dwc->pipe_clk);
if (ret)
goto disable_utmi_clk;
return 0;
disable_utmi_clk:
clk_disable_unprepare(dwc->utmi_clk);
disable_susp_clk:
clk_disable_unprepare(dwc->susp_clk);
disable_ref_clk:
clk_disable_unprepare(dwc->ref_clk);
disable_bus_clk:
......@@ -828,6 +840,8 @@ static int dwc3_clk_enable(struct dwc3 *dwc)
static void dwc3_clk_disable(struct dwc3 *dwc)
{
clk_disable_unprepare(dwc->pipe_clk);
clk_disable_unprepare(dwc->utmi_clk);
clk_disable_unprepare(dwc->susp_clk);
clk_disable_unprepare(dwc->ref_clk);
clk_disable_unprepare(dwc->bus_clk);
......@@ -1748,6 +1762,18 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
}
}
dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
if (IS_ERR(dwc->utmi_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
"could not get utmi clock\n");
}
dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
if (IS_ERR(dwc->pipe_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
"could not get pipe clock\n");
}
return 0;
}
......
......@@ -991,6 +991,8 @@ struct dwc3_scratchpad_array {
* @bus_clk: clock for accessing the registers
* @ref_clk: reference clock
* @susp_clk: clock used when the SS phy is in low power (S3) state
* @utmi_clk: clock used for USB2 PHY communication
* @pipe_clk: clock used for USB3 PHY communication
* @reset: reset control
* @regs: base address for our registers
* @regs_size: address space size
......@@ -1156,6 +1158,8 @@ struct dwc3 {
struct clk *bus_clk;
struct clk *ref_clk;
struct clk *susp_clk;
struct clk *utmi_clk;
struct clk *pipe_clk;
struct reset_control *reset;
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment