- Apr 04, 2024
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Detlev Casanova authored
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Signed-off-by: Jiajian Wu <jair.wu@rock-chips.com> Change-Id: I3103df9f379dfe98a4eb54dc5d3ce9f407038d8c Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Adds recommended N and Expected CTS Values for FRL Mode which defined in chapter 9.2.2 of HDMI Specification 2.1. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I1a21a111a65beeb024e5740c8bd231f9f534c1b5 Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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This patch workaround for no sound issue on Hisense TV which seems to need AUDI ACR packet when initial stage. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I192b631b29d33ad6571f70e062788c45b917803c Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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This patch wrap register access by lock which guarantee the clk enabled first. and remove the unused CLK status from CMN. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: Iba058ad08c71de0b118913216baec1886d8f3819 Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Keep ACR, AUDI, AUDS packet always on to make SINK device active for better compatibility and user experience. This also fix POP sound on some SINK devices which wakeup from suspend to active. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I6bb80a85a7ce0ba7046b4ac7bb7d75c38fcd95f3 Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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AUDI_CONTENTS0: { RSV, HB2, HB1, RSV } AUDI_CONTENTS1: { PB3, PB2, PB1, PB0 } AUDI_CONTENTS2: { PB7, PB6, PB5, PB4 } PB0: CheckSum PB1: | CT3 | CT2 | CT1 | CT0 | F13 | CC2 | CC1 | CC0 | PB2: | F27 | F26 | F25 | SF2 | SF1 | SF0 | SS1 | SS0 | PB3: | F37 | F36 | F35 | F34 | F33 | F32 | F31 | F30 | PB4: | CA7 | CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | PB5: | DM_INH | LSV3 | LSV2 | LSV1 | LSV0 | F52 | F51 | F50 | PB6~PB10: Reserved AUDI_CONTENTS0 default value defined by HDMI specification, and shall only be changed for debug purposes. So, we only configure payload byte from PB0~PB7(2 word total). Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: Idfbb34ff7f7069af4e73c6995f32eefa798a9450 Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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* LPCM: BPCUV insertion by hw * NLPCM/HBR: BPCUV insertion from stream when BPCUV is from stream, we should not enable hw channel status override which will replace CS with the hw one. This fixes DD+ bitstream. when BPCUV generated from HW, PBIT_FORCE_EN should be set for Parity bit calculated internally. This fixes no sound on some display devices. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I3aa0390d9dd7d217853394c74576749c36b84720 Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Change-Id: Idb62c2c9ea0d75d7090ec3e35c7742b0d42b3e43 Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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ACR located at Packet Scheduler which belongs to VIDQPCLK domain. So, the related clk should be enabled before register access. Actually, There are three CLK domain (AUDCLK, VIDQPCLK, LINKQPCLK) related to Audio. So, do check clk status before config audio. Maybe the better way should be spliting hdmi regmap into several parts which managed by related clk domain in future. e.g. devm_regmap_init_mmio_clk(dev, "aud", regs, AUD_REGBANK); devm_regmap_init_mmio_clk(dev, "vidqp", regs, VIDQP_REGBANK); devm_regmap_init_mmio_clk(dev, "linkqp", regs, LINKQP_REGBANK); ... Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: Ib497d92a73d99d9f38c4617f615f02c705b82ae7 Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I83e5558507994351b182a503325a56507f1867ee Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I41ceead79d46e08d5022bc1cc536af89437003a3 Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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This patch add support PATHx controls which allow user can select PATHx dynamically. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I9c3af821f9080ec2a07ed846ad059f68c82ec74f Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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This patch adds support for digital loopback mode select. lp mode2 swap: i2s sdi0_l <- i2s sdo0_l i2s sdi0_r <- codec sdo_r lp mode2: i2s sdi0_l <- codec sdo_l i2s sdi0_r <- i2s sdo0_r lp mode1: i2s sdi0_l <- codec sdo_l i2s sdi0_r <- codec sdo_r i2s sdi1_l <- i2s sdo0_l i2s sdi1_r <- i2s sdo0_r Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I14eb16667aca7c7c7e5f797b217adbcac2395f5a Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I9d0c2adbdffc268d88bac31c1db31507fd82661d Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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In hdmirx audio the cpu dai may act as slave And there also will be multi dai cells to select Signed-off-by: Shunhua Lan <lsh@rock-chips.com> Change-Id: I9b68a064204bb443b7e1e6fdc6e7f9e23b70e902 Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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this patch is used for rockchip HDMI audio output. Signed-off-by: XiaoTan Luo <lxt@rock-chips.com> Change-Id: I577179e7563ad241014d023da12af1e622e84c9a Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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- Mar 28, 2024
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Add initial support for the Synopsys DesignWare HDMI RX Controller Driver used by Rockchip RK3588. The driver supports: - HDMI 1.4b and 2.0 modes (HDMI 4k@60Hz) - RGB888, YUV422, YUV444 and YCC420 pixel formats - CEC - EDID configuration The hardware also has Audio and HDCP capabilities, but these are not yet supported by the driver. Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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Add device tree support for Synopsys DesignWare HDMI RX Controller. Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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Document bindings for the Synopsys DesignWare HDMI RX Controller. Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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Export hdmirx_biu soft reset id which is required by the hdmirx controller. Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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This drops to hs200 mode and 150Mhz as this is actually stable across eMMC modules. There exist some that are incompatible at higher rates with the rk3588 and to avoid your filesystem corrupting due to IO errors, be more conservative and reduce the max. speed. Signed-off-by: Carsten Haitzler <raster@rasterman.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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G610 Mali normally takes 2 regulators, but the devfreq implementation can only deal with one. Let's add a regulator coupler as done for mtk8183. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> [do s/Mediatek/Rockchip and rename mrc to rrc] Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Enable support for Mali CSF-based GPUs, which is found on recent ARM SoCs, such as Rockchip or Mediatek. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of the HDMI0 PHY PLL to support the additional display modes. Note this requires commit "drm/rockchip: vop2: Improve display modes handling on rk3588", which needs a rework to be upstreamable. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of the HDMI0 PHY PLL to support the additional display modes. Note this requires commit "drm/rockchip: vop2: Improve display modes handling on rk3588", which needs a rework to be upstreamable. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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The HDMI0 PHY can be used as a clock provider on RK3588, hence add the missing #clock-cells property.
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Add the necessary DT changes to enable HDMI0 on Rockchip RK3588 EVB1. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Add the necessary DT changes to enable HDMI0 on Rock 5B. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Add DT node for the HDMI0 bridge found on RK3588 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Document the DW HDMI TX Controller found on Rockchip RK3588 SoC. Since RK3588 uses different clocks than previous Rockchip SoCs and also requires a couple of reset lines and some additional properties, provide the required changes in the binding to be able to handle all variants. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Allow using the clock provided by HDMI0 PHY PLL to improve HDMI output support on RK3588 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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The HDMI PHY PLL can be used as an alternative dclk source to SoC CRU. It provides more accurate clock rates required to properly support various display modes, e.g. those relying on non-integer refresh rates. Also note this only works for HDMI 2.0 or bellow, e.g. cannot be used to support HDMI 2.1 4K@120Hz mode. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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The PHY can be used as a clock provider on RK3588, hence add the missing '#clock-cells' property. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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For upstreaming, this requires extending the standard PHY API to support HDMI configuration options [1]. Currently, the bus_width PHY attribute is used to pass clock rate and flags for 10-bit color depth, FRL and EARC. This is done by the HDMI bridge driver via phy_set_bus_width(). [1]: https://lore.kernel.org/all/59d5595a24bbcca897e814440179fa2caf3dff38.1707040881.git.Sandor.yu@nxp.com/ Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Improve HDMI0 clocking in order to support the additional display modes. Fixes: 5a028e8f ("drm/rockchip: vop2: Add support for rk3588") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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