- Jun 20, 2024
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Shreeya Patel authored
Add device tree support for Synopsys DesignWare HDMI RX Controller. Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com> Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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- Jun 19, 2024
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Shreeya Patel authored
Document bindings for the Synopsys DesignWare HDMI RX Controller. Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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Shreeya Patel authored
Add an entry for Synopsys DesignWare HDMI Receiver Controller Driver. Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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- May 28, 2024
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Add the documentation for VOP2 video ports reset clocks. One reset can be set per video port. Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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This adds the needed clock resets for all rk3588(s) based SOCs. Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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At the end of initialization, each VP clock needs to be reset before they can be used. Failing to do so can put the VOP in an undefined state where the generated HDMI signal is either lost or not matching the selected mode. Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Cristian Ciocaltea authored
RK3588 SoC updated the Synopsis DesignWare HDMI transmitter used in the older SoCs to Quad-Pixel (QP) variant, which is HDMI 2.1 compliant, while making use of a HDMI/eDP TX Combo PHY based on a Samsung IP block. Add just the basic support for now, i.e. RGB output up to 4K@30Hz, without audio, CEC or any of the HDMI 2.1 specific features. Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller supports the following features, among others: * Fixed Rate Link (FRL) * 4K@120Hz and 8K@60Hz video modes * Variable Refresh Rate (VRR) including Quick Media Switching (QMS), aka Cinema VRR * Fast Vactive (FVA), aka Quick Frame Transport (QFT) * SCDC I2C DDC access * TMDS Scrambler enabling 2160p@60Hz with RGB/YCbCr4:4:4 * YCbCr4:2:0 enabling 2160p@60Hz at lower HDMI link speeds * Multi-stream audio * Enhanced Audio Return Channel (EARC) Add driver to enable basic support, i.e. RGB output up to 4K@60Hz, without audio, CEC or any of the HDMI 2.1 specific features. Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
Document the DW HDMI TX Controller found on Rockchip RK3588 SoC. Since RK3588 uses different clocks than previous Rockchip SoCs and also requires a couple of reset lines and some additional properties, provide the required changes in the binding to be able to handle all variants. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The mpll_cfg, cur_ctr and phy_config members in struct dw_hdmi_plat_data are only used to configure the Synopsys PHYs supported internally by DW HDMI transmitter driver (gpu/drm/bridge/synopsys/dw-hdmi.c), via hdmi_phy_configure_dwc_hdmi_3d_tx(), which is further invoked from dw_hdmi_phy_init(). This is part of the internal dw_hdmi_synopsys_phy_ops struct, setup in dw_hdmi_detect_phy(). To handle vendor PHYs, the DW HDMI driver doesn't use the internal PHY ops, but expects the glue layers to provide the phy_ops and phy_name members of struct dw_hdmi_plat_data. Drop the unnecessary assignments of DW internal PHY related members from structs rk3228_hdmi_drv_data and rk3328_hdmi_drv_data, since both set the phy_force_vendor flag and provide the expected vendor PHY data. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The regulators are only enabled at bind() and disabled at unbind(), hence replace the boilerplate code by making use of devm_regulator_get_enable() helper. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
Make use of devm_clk_get_optional_enabled() to replace devm_clk_get() and clk_prepare_enable() for ref_clk and drop the now unnecessary calls to clk_disable_unprepare(). Additionally, use devm_clk_get_optional() helper for grf_clk to replace the open coding call to devm_clk_get() followed by the -ENOENT test. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
Prefer drm_{err|info|dbg}() over deprecated DRM_DEV_{ERROR|INFO|DEBUG}() logging macros. Conversion done with the help of the following semantic patch, followed by a few minor indentation adjustments: @@ identifier T; @@ ( -DRM_DEV_ERROR(T->dev, +drm_err(T, ...) | -DRM_DEV_INFO(T->dev, +drm_info(T, ...) | -DRM_DEV_DEBUG(T->dev, +drm_dbg(T, ...) ) Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
In preparation to support DW HDMI QP variant, add a new parameter to dw_hdmi_connector_create() which allows using a different drm_connector_funcs structure and move the function to the common header. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
In preparation to support DW HDMI QP variant and minimize code duplication, split dw_hdmi_setup() into a common dw_hdmi_prep_data() function to be shared by the two drivers. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
In preparation to support DW HDMI QP variant and minimize code duplication, split hdmi_av_composer() into a common dw_hdmi_prep_vmode() function to be shared by the two drivers. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
In preparation to support DW HDMI QP variant and minimize code duplication, split hdmi_config_AVI() into a common dw_hdmi_prep_avi_infoframe() function to be shared by the two drivers. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
In preparation to support DW HDMI QP variant, add a new parameter to dw_hdmi_i2c_adapter() which allows using a different i2c_algorithm and move the function to the common header. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
In preparation to add support for the HDMI 2.1 Quad-Pixel TX Controller, move structs and common function declarations to a new dw-hdmi-common.h header file. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
Make use of devm_clk_get_enabled() to replace devm_clk_get() and clk_prepare_enable() for isfr and iahb clocks, and drop the now unnecessary calls to clk_disable_unprepare(). Similarly, use devm_clk_get_optional_enabled() helper for cec clock, which additionally allows to remove the -ENOENT test. Moreover, the clock related members of struct dw_hdmi are not required anymore, hence drop them. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of the HDMI0 PHY PLL to support the additional display modes. Note this requires commit "drm/rockchip: vop2: Improve display modes handling on rk3588", which needs a rework to be upstreamable. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of the HDMI0 PHY PLL to support the additional display modes. Note this requires commit "drm/rockchip: vop2: Improve display modes handling on rk3588", which needs a rework to be upstreamable. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The HDMI0 PHY can be used as a clock provider on RK3588, hence add the missing #clock-cells property.
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Cristian Ciocaltea authored
Add the necessary DT changes to enable HDMI0 on Rockchip RK3588 EVB1. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
Add the necessary DT changes to enable HDMI0 on Rock 5B. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
Add DT node for the HDMI0 bridge found on RK3588 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Improve HDMI0 clocking in order to support the additional display modes. Fixes: 5a028e8f ("drm/rockchip: vop2: Add support for rk3588") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
Allow using the clock provided by HDMI0 PHY PLL to improve HDMI output support on RK3588 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The HDMI PHY PLL can be used as an alternative dclk source to SoC CRU. It provides more accurate clock rates required to properly support various display modes, e.g. those relying on non-integer refresh rates. Also note this only works for HDMI 2.0 or bellow, e.g. cannot be used to support HDMI 2.1 4K@120Hz mode. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The PHY can be used as a clock provider on RK3588, hence add the missing '#clock-cells' property. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
For upstreaming, this requires extending the standard PHY API to support HDMI configuration options [1]. Currently, the bus_width PHY attribute is used to pass clock rate and flags for 10-bit color depth, FRL and EARC. This is done by the HDMI bridge driver via phy_set_bus_width(). [1]: https://lore.kernel.org/all/59d5595a24bbcca897e814440179fa2caf3dff38.1707040881.git.Sandor.yu@nxp.com/ Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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- May 27, 2024
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Sebastian Reichel authored
When the Linux Type-C controller drivers probe, they requests a soft reset, which should result in the source restarting to send Source Capability messages again independently of the previous state. Unfortunately some USB PD sources do not follow the specification and do not send them after a soft reset when they already negotiated a specific contract before. The current way (and what is described in the specificiation) to resolve this problem is triggering a hard reset. But a hard reset is fatal on batteryless platforms powered via USB-C PD, since that removes VBUS for some time. Since this is triggered at boot time, the system will be stuck in a boot loop. Examples for platforms affected by this are the Radxa Rock 5B or the Libre Computer Renegade Elite ROC-RK3399-PC. Instead of directly trying a hard reset when no Source Capability message is send by the USB-PD source automatically, this changes the state machine to try explicitly asking for the capabilities by sending a Get Source Capability control message. For me this solves issues with 2 different USB-PD sources - a RAVPower powerbank and a Lemorele USB-C dock. Every other PD source I own follows the specification and automatically sends the Source Capability message after a soft reset, which works with or without this change. I decided against making this extra step limited to devices not having the self_powered flag set, since I don't see any huge drawbacks in this approach and it keeps the logic simpler. The worst case scenario would be a power source, which is really stuck. In that case the hard reset is delayed by another 310ms. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Sebastian Reichel authored
A USB-C hard reset involves removing the voltage from VBUS for some time. So basically it has the same effect as removing the USB-C plug for a short moment. If the machine is powered from the USB-C port and does not have a fallback supply (e.g. a battery), this will result in a full machine reset due to power loss. Ideally we want to avoid triggering a hard reset on these boards. A non-working USB-C port is probably better than unplanned reboots. But boards with a backup supply should do the hard reset to get everything working again. In theory it would be enough to check the self_powered property, but it seems the property might not be configured consistently enough in system firmwares. So let's start with just printing an error message when a hard reset is triggered on systems we expect to be affected. This at least makes debugging issues on affected systems easier without impacting unaffected systems too much. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Add initial support for the Synopsys DesignWare HDMI RX Controller Driver used by Rockchip RK3588. The driver supports: - HDMI 1.4b and 2.0 modes (HDMI 4k@60Hz) - RGB888, YUV422, YUV444 and YCC420 pixel formats - CEC - EDID configuration The hardware also has Audio and HDCP capabilities, but these are not yet supported by the driver. Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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Add device tree support for Synopsys DesignWare HDMI RX Controller. Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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Document bindings for the Synopsys DesignWare HDMI RX Controller. Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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This drops to hs200 mode and 150Mhz as this is actually stable across eMMC modules. There exist some that are incompatible at higher rates with the rk3588 and to avoid your filesystem corrupting due to IO errors, be more conservative and reduce the max. speed. Signed-off-by: Carsten Haitzler <raster@rasterman.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Also describe clkreq and wake signals in the PCIe pinmux used by the onboard LAN card. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Add rfkill support for bluetooth. Bluetooth support itself is still missing, but this ensures bluetooth can be powered off properly. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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With the proper GATE_LINK support, we no longer need to keep the linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL flag for them. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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