- Nov 16, 2024
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Cristian Ciocaltea authored
Enable use of HDMI 2.0 display modes, e.g. 4K@60Hz, by permitting TMDS character rates above the 340 MHz limit of HDMI 1.4b. Hence, add the required support for SCDC management, including the high TMDS clock ratio and scrambling setup. Additionally, filter out HDMI 2.1 display modes. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2. For now only HDMI0 output is supported, hence add the related PLL clock. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
Since commit c4b09c56 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI0 PHY. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The RK3588 specific implementation is currently quite limited in terms of handling the full range of display modes supported by the connected screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a few of them. Additionally, it doesn't cope well with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of HDMI0 PHY PLL as a more accurate DCLK source to handle all display modes up to 4K@60Hz. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
The if_pixclk_rate variable is not being used outside of the if-block in rk3588_calc_cru_cfg(), hence move the superfluous assignment from the first branch to the inner comment-block. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
On RK3588, HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 video ports 0, 1 and 2. Document the optional PLL clock properties corresponding to the two HDMI PHYs available on the SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
Enable Rockchip specific extensions for the Synopsys DesignWare HDMI QP driver. This is needed to provide HDMI output support for boards based on the RK3588 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Cristian Ciocaltea authored
In some cases, rk_hdptx_phy_runtime_resume() may be invoked before platform_set_drvdata() is executed in ->probe(), leading to a NULL pointer dereference when using the return of dev_get_drvdata(). Ensure platform_set_drvdata() is called before devm_pm_runtime_enable(). Reported-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Fixes: 553be283 ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Dividing a 64-bit integer prevents building this for 32-bit targets: ERROR: modpost: "__aeabi_uldivmod" [drivers/gpu/drm/rockchip/rockchipdrm.ko] undefined! As this function is not performance criticial, just Use the div_u64() helper. Fixes: 128a9bf8 ("drm/rockchip: Add basic RK3588 HDMI output support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241018151016.3496613-1-arnd@kernel.org Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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- Nov 15, 2024
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Stephen Rothwell authored
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
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https://github.com/Rust-for-Linux/linux.gitStephen Rothwell authored
# Conflicts: # rust/kernel/lib.rs # rust/kernel/task.rs # rust/kernel/types.rs # rust/macros/module.rs # scripts/Makefile.build
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Stephen Rothwell authored
Merge branch 'libnvdimm-for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git
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