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Sjoerd Simons
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- Apr 13, 2023
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Add support for the SATA0_0 port found on the RK3588 EVB1. The second port (SATA0_1) does not work, which matches the downstream behaviour. Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.com> -
Add all three SATA IP blocks to the RK3588 DT. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Add all 3 combo PHYs that can be found in RK3588. They are used for SATA, PCIe or USB3. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
The RK3588 has two reset lines for the combphy. One for the APB interface and one for the actual PHY. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Just like RK3568, the RK3588 has a DWC based AHCI controller. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
The pipe-phy syscon is used by rockchip,rk3588-naneng-combphy, which in turn is the PHY for USB3, PCIe and SATA. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Add support for RK3588 combo phy This is based on prior work from XiaoDong Huang and Peter Geis fixing this issue specifically for Rockchip 356x. Co-developed-by:
Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com> -
RK3568 Naneng Combo Phy driver can support RK3588 with the additional clocks and initial configuration, so add the compatible line. Signed-off-by:
Lucas Tanure <lucas.tanure@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Change-Id: I90aef072ef11729c8b1346aa4d8cdf792894f498 -
Enable USB2 (EHCI and OCHI mode) support for the Radxa ROCK 5 Model B. This adds USB support on the M.2 Key E, both USB2 ports and USB2 mode for the upper USB3 port (the one further away from the PCB). The lower USB3 (closer to the PCB) and the USB-C ports use the RK3588 USB TypeC host controller, which is not yet supported upstream. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Enable USB2 (EHCI and OCHI mode) support for the Rockchip RK3588 EVB1. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
This adds USB2 (EHCI & OHCI) ports including the related PHYs and GRF modules to the rk3588(s) device tree. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Simplify the code by directly getting the match data via device_get_match_data() instead of open coding its functionality. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Simplify phyclk handling by using devm_clk_get_optional_enabled to acquire and enable the optional clock. This also fixes a resource leak in driver remove path and adds proper error handling. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
On RK3588 some registers need to be tweaked to support waking up from suspend when a USB device is plugged into a port from a suspended PHY. Without this change USB devices only work when they are plugged at boot time. Apart from that it optimizes settings to avoid devices toggling between fullspeed and highspeed mode. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Add reset handling support, which is needed for proper operation with RK3588. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Add basic support for the USB2 PHY found in the Rockchip RK3588. Co-developed-by:
William Wu <william.wu@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
Add compatible for the USB2 phy in the Rockchip RK3588 SoC. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
The usb2phy is accessible via a syscon registers on RK3588, similar to rk3399. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Rockchip RK3588 OHCI requires 4 clocks to be enabled. Acked-by:
Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
Add compatible for RK3588 EHCI. As far as I know it's fully compatible with generic-ehci. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
Add compatible for RK3588 OHCI. As far as I know it's fully compatible with generic-ohci. Reviewed-by:
Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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- Apr 07, 2023
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On RK3588 it's also possible to power down the memory used by the particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds support for this feature. Tested-by:
Vincent Legoll <vincent.legoll@gmail.com>
Co-Developed-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
RK3588 has a couple of hardware blocks called Native Interface Unit (NIU) that gate the clocks to devices behind them. Effectively this means that some clocks require two parent clocks being enabled. Downstream implemented this by using a separate clock driver ("clk-link") for them, which enables the second clock using PM framework. In the upstream kernel we are currently missing support for the second parent. The information about it is in the GATE_LINK() macro as linkname, but that is not used. Thus the second parent clock is not properly enabled. So far this did not really matter, since these clocks are mostly required for the more advanced IP blocks, that are not yet supported upstream. As this is about to change we need a fix. There are three options available: 1. Properly implement support for having two parent clocks in the clock framework. 2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not disabled. This wastes some power, but keeps the hack contained within the clock driver. Going from this to the first solution is easy once that has been implemented. 3. Enabling the extra clock in the consumer driver. This leaks some implementation details into DT. This patch implements the second option as an intermediate solution until the first one is available. I used an alias for CLK_IS_CRITICAL, so that it's easy to see which clocks are not really critical once the clock framework supports a better way to implement this. Tested-by:Vincent Legoll <vincent.legoll@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
Fixed assigned clock rates. SCMI CPU clocks should default to 816 MHz, which is what the firmware defaults to. Additionally PLL_PPLL mistakenly was configured to 100MHz instead of 1.1 GHz. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Add missing, mandatory cache-level information for RK3588. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
The usual devm_regulator_get() call already handles "optional" regulators by returning a valid dummy and printing a warning that the dummy regulator should be described properly. This code open coded the same behaviour, but masked any errors that are not -EPROBE_DEFER and is quite noisy. This change effectively unmasks and propagates regulators errors not involving -ENODEV, downgrades the error print to warning level if no regulator is specified and captures the probe defer message for /sys/kernel/debug/devices_deferred. Fixes: 2e12f536 ("net: stmmac: dwmac-rk: Use standard devicetree property for phy regulator") Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.com> -
The clock requesting code is quite repetitive. Fix this by requesting the clocks via devm_clk_bulk_get_optional. The optional variant has been used, since this is effectively what the old code did. The exact clocks required depend on the platform and configuration. As a side effect this change adds correct -EPROBE_DEFER handling. Suggested-by:
Jakub Kicinski <kuba@kernel.org>
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Fixes: 7ad269ea ("GMAC: add driver for Rockchip RK3288 SoCs integrated GMAC")
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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- Mar 15, 2023
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Add regulator information for the CPU and enable the thermal sensor to have working cpu frequency scaling. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Add required bits for CPU frequency scaling to the Rockchip 3588 devicetree. This is missing the 2.4 GHz operating point for the big cpu clusters, since that does not work well on all SoCs. Downstream has a driver for PVTM, which reduces the requested frequencies based on (among other things) silicon quality. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
This is a heavily modified port from the downstream driver. Downstream used it for multiple rockchip generations, while upstream just used the generic cpufreq-dt driver so far. For rk3588 this is no longer good enough, since two regulators need to be controlled. Also during shutdown the correct frequency needs to be configured for the big CPU cores to avoid a system hang when firmware tries to bring them up at reboot time. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
This adds PMIC support for the RK3588 EVB. Signed-off-by:
shengfei Xu <xsf@rock-chips.com>
Co-developed-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
Update the defconfig for the new RK8XX MFD config name, which got split to add SPI support. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com>
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- Mar 07, 2023
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Add a new compatible for the thermal sensor device on RK3588 SoCs. Reviewed-by:
Heiko Stuebner <heiko@sntech.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
The RK3588 SoC has seven temperature sensor ADC channels: - Chip Center - CPU Cluster 1 (Dual A76 "Big" Cores) - CPU Cluster 2 (Dual A76 "Big" Cores) - CPU Cluster 0 (Quad A55 "Little" Cores) - Power Domain Center - Graphics Processing Unit - Neural Processing Unit Signed-off-by:
Finley Xiao <finley.xiao@rock-chips.com>
[rebase, squash fixes]
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
Dynamically allocate the sensors array based on the amount of platform sensors in preparation for rk3588 support, which needs 7 sensors. Reviewed-by:
Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
Replace the channel ID lookup table by a simple offset, since the channel IDs are consecutive. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Use dev_err_probe to simplify error printing in the driver's probe routine. Reviewed-by:
Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
By using devm_clk_get_enabled() the clock acquisition and enabling can be done in one step with automatic error handling. Reviewed-by:
Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
It's possible to directly get the match data in a generic way nowadays. Reviewed-by:
Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> -
Add rk806 support to the existing rk808 regulator driver. This has been implemented using shengfei Xu's rk806 specific driver from the vendor tree as reference. Co-Developed-by:
shengfei Xu <xsf@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Reviewed-by: Matti Vaittinen <mazziesaccount@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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