fixup: clk: rockchip: Add rk3576 clk support

- remove unused clk info struct
- remove unused grf reference in cru priv struct
- add ref_clk0_out_pll from header in latest vendor tag

arch/arm/include/asm/arch-rockchip/cru_rk3576.h

@@ -33,15 +33,8 @@ enum rk3576_pll_id {
 	PLL_COUNT,
 };
 
-struct rk3576_clk_info {
-	unsigned long id;
-	char *name;
-	bool is_cru;
-};
-
 struct rk3576_clk_priv {
 	struct rk3576_cru *cru;
-	struct rk3576_grf *grf;
 	ulong ppll_hz;
 	ulong gpll_hz;
 	ulong cpll_hz;
@@ -217,6 +210,18 @@ enum {
 	CLK_GMAC1_125M_DIV_SHIFT	= 0,
 	CLK_GMAC1_125M_DIV_MASK		= 0x1f << CLK_GMAC1_125M_DIV_SHIFT,
 
+	/* CRU_CLK_SEL33_CON */
+	REF_CLK0_OUT_PLL_SEL_SHIFT	= 8,
+	REF_CLK0_OUT_PLL_SEL_MASK	= 7 << REF_CLK0_OUT_PLL_SEL_SHIFT,
+	REF_CLK0_OUT_PLL_SEL_GPLL	= 0,
+	REF_CLK0_OUT_PLL_SEL_CPLL,
+	REF_CLK0_OUT_PLL_SEL_SPLL,
+	REF_CLK0_OUT_PLL_SEL_AUPLL,
+	REF_CLK0_OUT_PLL_SEL_LPLL,
+	REF_CLK0_OUT_PLL_SEL_OSC,
+	REF_CLK0_OUT_PLL_DIV_SHIFT	= 0,
+	REF_CLK0_OUT_PLL_DIV_MASK	= 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT,
+
 	/* CRU_CLK_SEL55_CON */
 	ACLK_BUS_ROOT_SEL_SHIFT		= 9,
 	ACLK_BUS_ROOT_SEL_MASK		= 1 << ACLK_BUS_ROOT_SEL_SHIFT,

drivers/clk/rockchip/clk_rk3576.c

@@ -2445,10 +2445,6 @@ static int rk3576_clk_probe(struct udevice *dev)
 	writel(0x001c000c, RK3576_CCI_GRF_BASE + 0x54);
 #endif
 
-	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	if (IS_ERR(priv->grf))
-		return PTR_ERR(priv->grf);
-
 	rk3576_clk_init(priv);
 
 	/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
@@ -2509,7 +2505,7 @@ U_BOOT_DRIVER(rockchip_rk3576_cru) = {
 	.name		= "rockchip_rk3576_cru",
 	.id		= UCLASS_CLK,
 	.of_match	= rk3576_clk_ids,
-	.priv_auto	 = sizeof(struct rk3576_clk_priv),
+	.priv_auto	= sizeof(struct rk3576_clk_priv),
 	.of_to_plat	= rk3576_clk_ofdata_to_platdata,
 	.ops		= &rk3576_clk_ops,
 	.bind		= rk3576_clk_bind,