Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Add support for rkrng variant, used by e.g. RK3528 and RK3576.

Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments for mainline.

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Enable clock stopping to gate clock during phase code change to ensure
glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
on RK3528.

POST_CHANGE_DLY
Time taken for phase switching and stable clock output.
- Less than 4-cycle latency

PRE_CHANGE_DLY
Maximum Latency specification between transmit clock and receive clock.
- Less than 4-cycle latency

TUNE_CLK_STOP_EN
Clock stopping control for Tuning and auto-tuning circuit. When enabled,
clock gate control output is pulled low before changing phase select
codes. This effectively stops the receive clock. Changing phase code
when clocks are stopped ensures glitch free phase switching.
- Clocks stopped during phase code change

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Add initial support for SDHCI controller in RK3528.

Only MMC Legacy and MMC High Speed (52MHz) mode is supported after this,
more work is needed to get the faster HS200/HS400/HS400ES modes working.

Variant tap and delay num is copied from vendor Linux tag
linux-6.1-stan-rkr5.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

RK3528 and RK3576 use different tap and delay num for cmdout and strbin.

Move tap and delay num for cmdout and strbin to driver data to prepare
for adding new SoCs.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Add pinctrl driver for RK3528.

Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with adjustments
to use regmap_update_bits().

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Add clock driver for RK3528.

Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments and fixes for mainline.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Add support for reading DRAM size information from PMUGRF os_reg18 reg.

Compared to most Rockchip SoCs the RK3528 use os_reg18 for DRAM info,
instead of os_reg2.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Rockchip RK3528 is a ARM-based SoC with quad-core Cortex-A53.

Add initial arch support for the RK3528 SoC.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.

Change to disable RX and/or TX delay and using zero as delay value.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.

Change to disable RX and/or TX delay and using zero as delay value.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

When MMC_SDHCI_SDMA=y or MMC_SDHCI_ADMA=y and PIO mode is used
dma_unmap_single() is called on an unmapped address, 0x0. This may
result in a Synchronous Abort:

  ## Checking hash(es) for Image atf-1 ... sha256+ OK
  CMD_SEND:16
                  ARG                      0x00000200
                  MMC_RSP_R1,5,6,7         0x00000900
  CMD_SEND:18
                  ARG                      0x00004005
  "Synchronous Abort" handler, esr 0x96000147
  elr: 00000000400015bc lr : 0000000040012b4c
  x 0: 0000000000008000 x 1: 0000000000092600
  x 2: 0000000000000040 x 3: 000000000000003f
  x 4: 0000000000000030 x 5: 0000000000000001
  x 6: 0000000000000001 x 7: 0000000000000000
  x 8: 000000000000000a x 9: 0000000000000090
  x10: 0000000043dffc68 x11: 0000000043c00440
  x12: 0000000043c00440 x13: ffffffffbfe00000
  x14: 000000000000031c x15: 0000000240000000
  x16: 000000004001145c x17: 0000000000000032
  x18: 0000000043dffef0 x19: 0000000043c00000
  x20: 0000000043dffbc8 x21: 0000000000000000
  x22: 00000000000f3d95 x23: 0000000000000002
  x24: 0000000000000493 x25: 0000000000092600
  x26: 0000000000000001 x27: 0000000000000001
  x28: 0000000000000008 x29: 0000000043dffab0

  Code: d2800082 9ac32042 d1000443 8a230000 (d5087620)
  Resetting CPU ...

  resetting ...

Fix this by only dma_unmap_single() when DMA mode is used and
sdhci_prepare_dma() has been called to map host->start_addr.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
recalculated so it remain unchanged. Add missing GPIO3-B1 to GPIO3-B7
pinmux data to rk3328_mux_recalced_data as mux register offset for these
pins does not follow rockchip convention.

This matches changes in following Linux commits:
- e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins")
- 5ef6914e0bf5 ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins")
- 128f71fe014f ("pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pins")

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Remove the rockchip,rk3399-dwc3 compatible from the dwc3-of-simple
driver now that all boards have changed to use the dwc3-generic driver.

Also remove the amlogic,meson-gxl-dwc3 compatible, it is no longer in
use by any device tree in mainline linux or U-Boot.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

emul_rtc_probe() is not called from anywhere else that's why make it
static. Issue is reported by build with W=1.

Signed-off-by: Michal Simek <michal.simek@amd.com>

Support phy io micro voltage setting for NPCM8XX rgmii
interface.

Signed-off-by: Michael Chang <zhang971090220@gmail.com>

This patch add support to read register base address by name if
provided.

Also devfdt_get_addr_* is changed to dev_read_addr_* to support DT
live tree.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

The reg-names in mt7988.dtsi have no _base suffix. Remove the suffix
will also make it match upstream linux format.

Fixes: 8c2cb748 (pinctrl: mediatek: mt7988: rename reg-names to upstream linux format)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

in linux we have the option to create the name of a led
optionally through the following properties:

- function
- color
- function-enumerator

This patch adds support for parsing this properties if there
is no label property.

The led name is created in led_post_bind() and we need some
storage place for it. Currently this patch prevents to use
malloc() instead it stores the name in new member :

        char name[LED_MAX_NAME_SIZE];

of struct led_uc_plat. While at it append led tests for the
new feature.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

Fixes annoying warnings of the following type when built with W=1 (for
each file including fpga.h):

      CC      drivers/fpga/fpga.o
    In file included from /mnt/data/adahl/src/u-boot/include/xilinx.h:7,
                     from /mnt/data/adahl/src/u-boot/drivers/fpga/fpga.c:10:
    /mnt/data/adahl/src/u-boot/include/fpga.h:61:1: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]
       61 | const fpga_desc *const fpga_get_desc(int devnum);
          | ^~~~~
    /mnt/data/adahl/src/u-boot/include/fpga.h:81:1: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]
       81 | const fpga_desc *const fpga_validate(int devnum, const void *buf,
          | ^~~~~
    /mnt/data/adahl/src/u-boot/drivers/fpga/fpga.c:36:1: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]
       36 | const fpga_desc *const fpga_get_desc(int devnum)
          | ^~~~~
    /mnt/data/adahl/src/u-boot/drivers/fpga/fpga.c:53:1: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]
       53 | const fpga_desc *const fpga_validate(int devnum, const void *buf,
          | ^~~~~

Do some type and cast cleanup on that fpga_desc type while at it.

Link: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wignored-qualifiers


Signed-off-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20250121162213.1477506-1-ada@thorsis.com


Signed-off-by: Michal Simek <michal.simek@amd.com>

Add missing prototype to fix the sparse warning,
warning: no previous prototype for 'cadence_qspi_flash_reset'
[-Wmissing-prototypes].

Fixes: 6d234a79 ("cadence_qspi: Refactor the flash reset functionality")
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250122135334.1201562-1-venkatesh.abbarapu@amd.com


Signed-off-by: Michal Simek <michal.simek@amd.com>

If the least significant bit of the address is set to one when
using the DDR protocol for data transfer then the results are
indeterminate for few flash devices. To fix this the least
significant bit of the address is set to zero.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250106095120.800753-1-padmarao.begari@amd.com


Signed-off-by: Michal Simek <michal.simek@amd.com>

Update the debug() print, use __func__ to always print matching
function name, and also print bus name in case there are multiple
busses.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>

Replace ifdeffery with plain debug() function call. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>

Explicitly flush icache on the CR52 core before jumping to the next
stage software to make sure it does not contain any invalid content.
Explicitly flash and invalidate dcache on the CA76 core both over the
trampoline buffer and over the CR52 firmware, and then trigger full
system synchronization, to make sure the data surely land in DRAM,
from where the CR52 can surely pick them up.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>

VPL may want to use driver model for MMC even if TPL does not. Update
the rule in this driver to support that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

Use the driver macros so that the driver appears in the
linker list.

Reported-by: Simon Glass <sjg@chromium.org>
Fixes: 732f01aa ("pinctrl: starfive: Add StarFive JH7110 driver")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>

This patch fixed the following coding style suggested by checkpatch.pl:
1. Use tab instead of space
2. Use BIT() instead of <<
3. Use mdelay for long time delay
4. Remove useless parenthesises

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

Update mt7981 pinctrl driver based on upstream kernel

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

The SCSI specification originally required that the second
Command Data Byte contain the LUN value in its high-order bits,
but this field has been marked as reserved since the SCSI-3 spec
from 1996.

Some vendors uses this byte to pass vendor specific data,
and specifying the LUN can trigger strange behaviors.
For the record, this happened on an UFS device where LUN0 was
working perfectly and reading the other LUNs would get the last
buffer data that was read for LUN0, making this issue very very
hard to debug.

It's sane to assume U-Boot will probably never encounter
an SCSI-2 multi-LUN device, if somehow it happens the enquiry
command would need to get the SCSI level to handle this case.

The Linux fix was added in [1] to fix the exact same issue.

[1] https://lore.kernel.org/all/Pine.LNX.4.44L0.1409021108380.2308-100000@iolanthe.rowland.org/



Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

If CONFIG_SYS_64BIT_LBA is enable, following compilation warning is
triggered:

 CC      drivers/fastboot/fb_mmc.o
../drivers/fastboot/fb_mmc.c: In function 'fb_mmc_erase_mmc_hwpart':
../drivers/fastboot/fb_mmc.c:215:35: warning: format '%lu' expects
argument of type 'long unsigned int', but argument 2 has type
'long long unsigned int' [-Wformat=]
  215 |         printf("........ erased %lu bytes from mmc hwpart[%u]\n",
      |                                 ~~^
      |                                   |
      |                                   long unsigned int
      |                                 %llu
  216 |                dev_desc->lba * dev_desc->blksz, dev_desc->hwpart);
      |                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      |                              |
      |                              long long unsigned int
../drivers/fastboot/fb_mmc.c: In function 'fb_mmc_boot_ops':
../drivers/fastboot/fb_mmc.c:261:42: warning: format '%lu' expects
argument of type 'long unsigned int', but argument 2 has type
'long long unsigned int' [-Wformat=]
  261 |                 printf("........ wrote %lu bytes to EMMC_BOOT%d\n",
      |                                        ~~^
      |                                          |
      |                                          long unsigned int
      |                                        %llu
  262 |                        blkcnt * blksz, hwpart);
      |                        ~~~~~~~~~~~~~~
      |                               |
      |                               long long unsigned int

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Some dt-binding headers mask the upstream ones which can lead to build
failures, or worse: super weird bugs, if they get out of sync.

Remove these headers so our devicetree and binding headers will both be
in sync with upstream.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

The TI DP83822 does have support for configurable RGMII RX/TX clock
shift, add support for parsing DT properties which describe the RX/TX
clock shift configuration and configuration of the matching bits in
RCSR register.

The shift is only configurable on DP83822, the other PHYs supported
by this PHY driver, namely DP83825/DP83826 variants, do not implement
this functionality and the RCSR bits used to configure the clock shift
are missing from those PHYs.

The shift is configurable separately for RX and TX path. Each path can
either enable the shift or disable the shift using single bit. In case
the shift is disabled, a delay of 0ns is added to the path, otherwise
a delay of 3.5ns is added to the path.

Note that the two RCSR bits 11 and 12 have inverted logic, RCSR bit 12
enables RX internal shift when SET, while RCSR bit 11 enables TX shift
when UNSET.

Signed-off-by: Marek Vasut <marex@denx.de>

This patch adds eMMC/SD support for MT7987 SoC

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

This patch adds pinctrl and gpio support for MT7987 SoC

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

This patch adds clock driver support for MediaTek MT7987 SoC

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

These functions can be static as they are referenced only in this file.
Make them static. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>