Add a binding for the MediaTek TinySYS MHU mailbox, used for IPC
with the TinySYS hardware integrated in various MediaTek SoCs.

This mailbox handles a custom MHU enabling communication through
the TinySYS SCMI protocol.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a real driver for the Display Stream Compression (DSC) Display
Controller IP, implementing support for DSC v1.1 to v1.2.

In order to do this, it was necessary to remove the basic DSC IP
bypass setup from mtk_ddp_comp: this functionality is retained in
the new mtk_disp_dsc driver, which checks if DSC was actually
requested by other components (with the only one that currently
supports this being DSI) and, if not, it will set BYPASS mode in
the DSC IP.

Like before, the BYPASS mode is set before starting the DSC IP,
but unlike before, this is being done in the component start
callback instead of the config one.
Notably, the config callback is called by mtk_crtc always
immediately before the calling start callback, so the order of
register writes is retained.
The only real difference is that now this is being done through
CPU writes instead of CMDQ, but since that's called only once
and since it's just three registers, the performance impact will
not be minimal and not even measurable.

As anticipated, DSC handling was also introduced in the mtk_dsi
driver: when performing dsi_host_attach, the driver now checks
if the DSI panel adds the DSC configuration structure to the
mipi_dsi_device structure and, if it does, it will store a
pointer in the driver-local mtk_dsi structure's `dsc` member.

The DSI driver will then check whether the DSC configuration
that comes from the panel is valid (in regard to MediaTek DSI)
and will call the DRM API's DSC helpers to calculate and set
all of the const and RC parameters for the actual DSC setup.

For the time being, even though the latest MediaTek SoCs do
support DSC v1.2, only DSC v1.1 pre-scr support is implemented
as an initial contribution (which is rather big, and 1.2 would
make it even bigger - but that can anyway be implemented later).

As a last step for validation of DSC parameters in DSI, a check
for the hdisplay against DSC slice sidth and one for vdisplay
against DSC slice height was added to the mode_valid callback,
making sure that H/V are, as expected, multiples of slice W/H.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a new driver for DSI panels over the Samsung S6E3FC3 Display
Driver IC.
This includes support for various panels, each found in multiple
smartphones; Included panels are:
 - Samsung AMS643YE05 6.43" (OnePlus/Oppo/Realme)
 - Samsung AMS646YD04 6.5" (Samsung smartphones)
 - Samsung AMS667YM01 6.7" (Samsung smartphones)

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Samsung S6E3FC3 is a Display DriverIC suitable for driving LCD
MIPI-DSI AMOLED panels, usually with a resolution of 1080x2400
at 60Hz or 90Hz, mainly found in smartphones from various
manufacturers such as Oppo, OnePlus, Samsung Mobile and others.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

In case the controller uses the top_base iospace, most register
read/writes can be changed from multiple RWs to a single read
and a single write.

Where possible, and where it makes sense, aggregate the multiple
reads and writes to just one.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Instead of reading and writing the LOOP_TEST_CONTROL register for
each set or cleared bit, read it once, modify the contents in a
local variable, and then write once.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Instead of continuously reading and writing to the patch bit 1/2
registers, prepare the final values to write to those and write
just once per register during the setup phase.

This makes the driver slightly smaller and also slightly improves
the execution time of the msdc_init_hw function, called not only
at probe time, but also when resuming from system suspend.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

In preparation for cleaning up the msdc_init_hw register setting
for the patch bit registers, add the necessary definitions for
bits in the MSDC_PATCH_BIT and MSDC_PATCH_BIT1 registers and use
them in place of "magic numbers" writes during initialization.

This commit brings no functional differences.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Remove support for the MediaTek MT8173 MTCMOS from this old and
deprecated power domains driver.

The MT8173 SoC was migrated to mtk-pm-domains a lot of time ago
(many kernel releases ago) because it was not working correctly
in this driver, so removing support from there is not breaking
anything - as support for this SoC was not realy functional in
this driver's code.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a basic driver for the Write DMA Engine and initial compatible
for the MediaTek Dimensity 1200 MT6893, and hook it up to the
mtk_ddp_comp and mtk_drm_drv in order for it to probe.

This display controller component is used to enable pipelines for
driving command mode DSI displays.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Multiple MediaTek SoCs have the Write DMA hardware in their Display
Controller: add the missing compatibles for Dimensity 1200 (MT6893)
and for Kompanio 500/520/820/1200 (MT8183/MT8186/MT8192/MT8195).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a compatible string for the MediaTek Dimensity 1200 (MT6893)
SoC: this chip integrates a MediaTek generic T-PHY version 2.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add support for the MediaTek Dimensity 1200 (MT6893) SoC: the DSI
PHY found in this chip is fully compatible with the one found in
the MT8183 SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add support for the MediaTek Dimensity 1200 (MT6893) SoC; this
chip's multiple I2C controller instances are fully compatible
with the ones found in the MT8192 SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a compatible string for the Display Controller PWM IP found in
the MediaTek Dimensity 1200 (MT6893) SoC, which is compatible with
the one found in MT8183.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a compatible for the MediaTek Dimensity 1200 (MT6893) SoC.
All of the MMC/SD controllers in this chip are compatible with
the ones found in MT8183, but do also make use of an optional
crypto clock when enabling HW disk encryption.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a compatible string for the MediaTek Dimensity 1200 (MT6893)
SoC, which UART IPs are fully compatible with MT6577.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a compatible for the Dimensity 1200 (MT6893) SoC; The AUXADC
IP in this chip is fully compatible with the one found in MT8173.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a compatible string for the scpsys block found in the MediaTek
Dimensity 1200 (MT6893) SoC.

Sigend-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a compatible string for the MediaTek Dimensity 1200 (MT6893)
SoC using MT8195 as a fallback, and add a header for the GCE
mailbox found in MT6893.

Similarly to MT8195, this SoC has two GCE hardware instances, but
the event values are different (hence requiring its own header).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add support for the MediaTek Dimensity 1200 (MT6893) SoC's DVFSRC
v2 hardware: the only difference between this and the only other
supported DVFSRCv2 SoC (MT8195) is the VCore-DRAM OPP array.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Rename the MT8183 and MT8195 bandwidth constraints data structure
to, respectively, dvfsrc_bw_constr_v1 and dvfsrc_bw_constr_v2, as
the actual constraints are depending on the DVFSRC version rather
than on the SoC.

While at it, to prepare for adding a new SoC, also move the two
structures at the start of the platform data code section.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

The MediaTek Dimensity 1200 (MT6893) features the same DVFSRC
regulators as the other currently supported SoCs, but with a
different select value: add an array describing the possible
voltages for the VCORE and VSCP regulators, and assign it to
a new compatible for this SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a compatible for the MediaTek Dimensity 1200 (MT6893) SoC's
regulators over DVFSRC.
This SoC uses different values for the vsel, hence it is not
compatible with the currently supported ones.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a compatible for the MediaTek Dimensity 1200 (MT6893) SoC's
DVFSRC hardware, introducing capability to communicate with it.

Even though this SoC uses the same basic version of the DVFSRC
IP as MT8195, the vcore-vdram parameters are different, hence
no fallback compatibility is possible.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add support for the two MM IOMMUs found in the MediaTek Dimensity
1200 (MT6893) SoC, used for display, camera, imgsys and vpu.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add binding for the MediaTek Dimensity 1200 (MT6893) SoC's
MultiMedia (MM) IOMMU.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add the necessary platform data to enable support for the SMI
found on the MediaTek Dimensity 1200 (MT6893) SoC

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add support for the Smart Multimedia Interface's Common and Local
Arbiter HW as found in the MediaTek Dimensity 1200 (MT6893) SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a MMSYS table for the display controller found in the
MediaTek Dimensity 1200 (MT6893) SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add mutex tables for the display components to add support for
the mute bits configuration of the display controller found in
the MediaTek Dimensity 1200 (MT6893) SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add support for the peripheral (imp_iic_wrap for i2c, scp_adsp for
the System Companion Processor's AudioDSP clock output) and
multimedia clock drivers (Multimedia Data Path, Display, GPU and
video encoders/decoders) that are present in the MediaTek
Dimensity 1200 (MT6893) SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add drivers for the main system clock controllers present in the
MediaTek Dimensity 1200 (MT6893) SoC.
This adds support for the PLLs and topck/infra muxes and gates.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>