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Unverified Commit 29f15703 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt8390-genio-700-evk: Add Display on DSI0 


Configure the DSI0 display pipeline and add regulator, pinctrl
and display node to enable the Startek KD070FHFID078 panel found
on the MediaTek Genio 700 EVK.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 2ea29d73
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arch/arm64/boot/dts/mediatek/mt8188.dtsi
+ 140
− 0
View file @ 29f15703
......@@ -2831,6 +2831,23 @@ ovl0: ovl@1c000000 {
iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ovl0_in: endpoint { };
};
port@1 {
reg = <1>;
ovl0_out: endpoint {
remote-endpoint = <&rdma0_in>;
};
};
};
};
rdma0: rdma@1c002000 {
......@@ -2841,6 +2858,25 @@ rdma0: rdma@1c002000 {
iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
rdma0_in: endpoint {
remote-endpoint = <&ovl0_out>;
};
};
port@1 {
reg = <1>;
rdma0_out: endpoint {
remote-endpoint = <&color0_in>;
};
};
};
};
color0: color@1c003000 {
......@@ -2850,6 +2886,25 @@ color0: color@1c003000 {
interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
color0_in: endpoint {
remote-endpoint = <&rdma0_out>;
};
};
port@1 {
reg = <1>;
color0_out: endpoint {
remote-endpoint = <&ccorr0_in>;
};
};
};
};
ccorr0: ccorr@1c004000 {
......@@ -2859,6 +2914,25 @@ ccorr0: ccorr@1c004000 {
interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ccorr0_in: endpoint {
remote-endpoint = <&color0_out>;
};
};
port@1 {
reg = <1>;
ccorr0_out: endpoint {
remote-endpoint = <&aal0_in>;
};
};
};
};
aal0: aal@1c005000 {
......@@ -2868,6 +2942,25 @@ aal0: aal@1c005000 {
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
aal0_in: endpoint {
remote-endpoint = <&ccorr0_out>;
};
};
port@1 {
reg = <1>;
aal0_out: endpoint {
remote-endpoint = <&gamma0_in>;
};
};
};
};
gamma0: gamma@1c006000 {
......@@ -2877,6 +2970,23 @@ gamma0: gamma@1c006000 {
interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
gamma0_in: endpoint {
remote-endpoint = <&aal0_out>;
};
};
port@1 {
reg = <1>;
gamma0_out: endpoint { };
};
};
};
dither0: dither@1c007000 {
......@@ -2886,6 +2996,21 @@ dither0: dither@1c007000 {
interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dither0_in: endpoint { };
};
port@1 {
reg = <1>;
dither0_out: endpoint { };
};
};
};
disp_dsi0: dsi@1c008000 {
......@@ -2968,6 +3093,21 @@ postmask0: postmask@1c01a000 {
interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
postmask0_in: endpoint { };
};
port@1 {
reg = <1>;
postmask0_out: endpoint { };
};
};
};
vdosys0: syscon@1c01d000 {
......
arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
+ 137
− 8
View file @ 29f15703
......@@ -23,6 +23,7 @@ / {
"mediatek,mt8188";
aliases {
dsi0 = &disp_dsi0;
ethernet0 = &eth;
i2c0 = &i2c0;
i2c1 = &i2c1;
......@@ -36,6 +37,15 @@ aliases {
serial0 = &uart0;
};
backlight_lcm1: backlight-lcm1 {
compatible = "pwm-backlight";
brightness-levels = <0 1023>;
default-brightness-level = <576>;
num-interpolated-steps = <1023>;
power-supply = <&reg_vsys>;
pwms = <&disp_pwm1 0 500000>;
};
chosen {
stdout-path = "serial0:921600n8";
};
......@@ -226,6 +236,28 @@ usb_p2_vbus: regulator-9 {
regulator-max-microvolt = <5000000>;
enable-active-high;
};
lcm1_iovcc: regulator-vio18-lcm1 {
compatible = "regulator-fixed";
regulator-name = "vio18_lcm1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
gpio = <&pio 111 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dsi0_vreg_en_pins>;
vin-supply = <&reg_vsys>;
};
lcm1_vddp: regulator-vsys-lcm1 {
compatible = "regulator-fixed";
regulator-name = "vsys_lcm1";
regulator-min-microvolt = <4200000>;
regulator-max-microvolt = <4200000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&reg_vsys>;
};
};
&adsp {
......@@ -238,6 +270,67 @@ &afe {
status = "okay";
};
&disp_dsi0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
panel@0 {
compatible = "startek,kd070fhfid078", "himax,hx8279";
reg = <0>;
backlight = <&backlight_lcm1>;
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
iovcc-supply = <&lcm1_iovcc>;
vdd-supply = <&lcm1_vddp>;
pinctrl-names = "default";
pinctrl-0 = <&panel_default_pins>;
port {
dsi_panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dither0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&dsi_panel_in>;
};
};
};
};
&disp_pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&disp_pwm1_pins>;
status = "okay";
};
&dither0_in {
remote-endpoint = <&postmask0_out>;
};
&dither0_out {
remote-endpoint = <&dsi0_in>;
};
&gamma0_out {
remote-endpoint = <&postmask0_in>;
};
&gpu {
mali-supply = <&mt6359_vproc2_buck_reg>;
status = "okay";
......@@ -313,6 +406,10 @@ &mfg1 {
domain-supply = <&mt6359_vsram_others_ldo_reg>;
};
&mipi_tx_config0 {
status = "okay";
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
......@@ -422,6 +519,10 @@ &mt6359codec {
mediatek,mic-type-1 = <3>; /* DCC */
};
&ovl0_in {
remote-endpoint = <&vdosys0_ep_main>;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins_default>;
......@@ -460,6 +561,12 @@ pins-cmd-dat {
};
};
disp_pwm1_pins: disp-pwm1-pins {
pins-pwm {
pinmux = <PINMUX_GPIO30__FUNC_O_DISP_PWM1>;
};
};
dptx_pins: dptx-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>;
......@@ -780,20 +887,22 @@ pins-dat1 {
};
};
panel_default_pins: panel-default-pins {
pins-dcdc {
pinmux = <PINMUX_GPIO45__FUNC_B_GPIO45>;
output-low;
};
pins-en {
dsi0_vreg_en_pins: dsi0-vreg-en-pins {
pins-pwr-en {
pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>;
output-low;
};
};
panel_default_pins: panel-default-pins {
pins-rst {
pinmux = <PINMUX_GPIO25__FUNC_B_GPIO25>;
output-high;
output-low;
};
pins-en {
pinmux = <PINMUX_GPIO45__FUNC_B_GPIO45>;
output-low;
};
};
......@@ -955,6 +1064,14 @@ power-key {
};
};
&postmask0_in {
remote-endpoint = <&gamma0_out>;
};
&postmask0_out {
remote-endpoint = <&dither0_in>;
};
&scp {
memory-region = <&scp_mem>;
status = "okay";
......@@ -1007,6 +1124,18 @@ &uart2 {
status = "okay";
};
&vdosys0 {
port {
#address-cells = <1>;
#size-cells = <0>;
vdosys0_ep_main: endpoint@0 {
reg = <0>;
remote-endpoint = <&ovl0_in>;
};
};
};
&u3phy0 {
status = "okay";
};
......
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