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Unverified Commit 5fd858bb authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipeline


This board can use a MIPI-DSI panel on the DSI0 connector: in
preparation for adding an overlay for the Radxa Display 8HD,
add a pipeline connecting VDOSYS0 components to DSI0.

This pipeline remains disabled by default, as it is expected
to be enabled only by a devicetree overlay that declares the
actual DSI panel node, completing the graph.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 9de2eaf8
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......@@ -186,6 +186,10 @@ &cpu7 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&dither0_out {
remote-endpoint = <&dsi0_in>;
};
&dpi1 {
status = "okay";
};
......@@ -198,6 +202,29 @@ &dpi1_out {
remote-endpoint = <&hdmi0_in>;
};
&dsi0 {
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dither0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint { };
};
};
};
&eth {
phy-mode = "rgmii-rxid";
phy-handle = <&rgmii_phy>;
......
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