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Unverified Commit 7a6b5c34 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno
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soc: mediatek: mmsys: Migrate all tables to MMSYS_ROUTE() macro 


Now that all of the mmsys routing tables have been fixed,
migrate all of them to use the MMSYS_ROUTE() macro: this
will make sure that future additions to any of the tables
for the currently supported SoCs are compile-time sanity
checked, greatly reducing room for (way too common) mistakes.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 57fc0370
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drivers/soc/mediatek/mt8167-mmsys.h
+ 15
− 21
View file @ 7a6b5c34
......@@ -14,27 +14,21 @@
#define MT8167_DSI0_SEL_IN_RDMA0 0x1
static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
OVL0_MOUT_EN_COLOR0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0,
MT8167_DITHER_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
COLOR0_SEL_IN_OVL0
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0,
MT8167_DSI0_SEL_IN_RDMA0
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0,
MT8167_RDMA0_SOUT_DSI0
},
MMSYS_ROUTE(OVL0, COLOR0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
OVL0_MOUT_EN_COLOR0),
MMSYS_ROUTE(DITHER0, RDMA0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0,
MT8167_DITHER_MOUT_EN_RDMA0),
MMSYS_ROUTE(OVL0, COLOR0,
MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
COLOR0_SEL_IN_OVL0),
MMSYS_ROUTE(RDMA0, DSI0,
MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0,
MT8167_DSI0_SEL_IN_RDMA0),
MMSYS_ROUTE(RDMA0, DSI0,
MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0,
MT8167_RDMA0_SOUT_DSI0),
};
#endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */
drivers/soc/mediatek/mt8173-mmsys.h
+ 42
− 57
View file @ 7a6b5c34
......@@ -33,63 +33,48 @@
#define MT8173_RDMA0_SOUT_COLOR0 BIT(0)
static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
MT8173_OVL0_MOUT_EN_COLOR0, MT8173_OVL0_MOUT_EN_COLOR0
}, {
DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN,
MT8173_OD0_MOUT_EN_RDMA0, MT8173_OD0_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN,
MT8173_UFOE_MOUT_EN_DSI0, MT8173_UFOE_MOUT_EN_DSI0
}, {
DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN,
MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
MT8173_COLOR0_SEL_IN_OVL0, MT8173_COLOR0_SEL_IN_OVL0
}, {
DDP_COMPONENT_AAL0, DDP_COMPONENT_COLOR0,
MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN,
MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN,
MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */
}, {
DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
MT8173_DISP_REG_CONFIG_DSI0_SEL_IN,
MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN,
MT8173_OVL1_MOUT_EN_COLOR1, MT8173_OVL1_MOUT_EN_COLOR1
}, {
DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN,
MT8173_GAMMA_MOUT_EN_RDMA1, MT8173_GAMMA_MOUT_EN_RDMA1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,
RDMA1_SOUT_MASK, RDMA1_SOUT_DPI0
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN,
COLOR1_SEL_IN_OVL1, COLOR1_SEL_IN_OVL1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8173_DISP_REG_CONFIG_DPI_SEL_IN,
MT8173_DPI0_SEL_IN_MASK, MT8173_DPI0_SEL_IN_RDMA1
}
MMSYS_ROUTE(OVL0, COLOR0,
MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8173_OVL0_MOUT_EN_COLOR0,
MT8173_OVL0_MOUT_EN_COLOR0),
MMSYS_ROUTE(OD0, RDMA0,
MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, MT8173_OD0_MOUT_EN_RDMA0,
MT8173_OD0_MOUT_EN_RDMA0),
MMSYS_ROUTE(UFOE, DSI0,
MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8173_UFOE_MOUT_EN_DSI0,
MT8173_UFOE_MOUT_EN_DSI0),
MMSYS_ROUTE(COLOR0, AAL0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, MT8173_COLOR0_SOUT_MERGE,
0 /* SOUT to AAL */),
MMSYS_ROUTE(RDMA0, UFOE,
MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8173_RDMA0_SOUT_COLOR0,
0 /* SOUT to UFOE */),
MMSYS_ROUTE(OVL0, COLOR0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8173_COLOR0_SEL_IN_OVL0,
MT8173_COLOR0_SEL_IN_OVL0),
MMSYS_ROUTE(AAL0, COLOR0,
MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, MT8173_AAL_SEL_IN_MERGE,
0 /* SEL_IN from COLOR0 */),
MMSYS_ROUTE(RDMA0, UFOE,
MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8173_UFOE_SEL_IN_RDMA0,
0 /* SEL_IN from RDMA0 */),
MMSYS_ROUTE(UFOE, DSI0,
MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, MT8173_DSI0_SEL_IN_UFOE,
0 /* SEL_IN from UFOE */),
MMSYS_ROUTE(OVL1, COLOR1,
MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, MT8173_OVL1_MOUT_EN_COLOR1,
MT8173_OVL1_MOUT_EN_COLOR1),
MMSYS_ROUTE(GAMMA, RDMA1,
MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, MT8173_GAMMA_MOUT_EN_RDMA1,
MT8173_GAMMA_MOUT_EN_RDMA1),
MMSYS_ROUTE(RDMA1, DPI0,
MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DPI0),
MMSYS_ROUTE(OVL1, COLOR1,
MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
COLOR1_SEL_IN_OVL1),
MMSYS_ROUTE(RDMA1, DPI0,
MT8173_DISP_REG_CONFIG_DPI_SEL_IN, MT8173_DPI0_SEL_IN_MASK,
MT8173_DPI0_SEL_IN_RDMA1),
};
#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */
drivers/soc/mediatek/mt8183-mmsys.h
+ 21
− 29
View file @ 7a6b5c34
......@@ -28,35 +28,27 @@
#define MT8183_MMSYS_SW0_RST_B 0x140
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
MT8183_OVL0_MOUT_EN_OVL0_2L
}, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
}, {
DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0
}, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
MT8183_DISP_PATH0_SEL_IN_OVL0_2L
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
MT8183_DPI0_SEL_IN_RDMA1
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
MT8183_RDMA0_SOUT_COLOR0
}
MMSYS_ROUTE(OVL0, OVL_2L0,
MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
MT8183_OVL0_MOUT_EN_OVL0_2L),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
MT8183_OVL0_2L_MOUT_EN_DISP_PATH0),
MMSYS_ROUTE(OVL_2L1, RDMA1,
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1),
MMSYS_ROUTE(DITHER0, DSI0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
MT8183_DISP_PATH0_SEL_IN_OVL0_2L),
MMSYS_ROUTE(RDMA1, DPI0,
MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
MT8183_DPI0_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
MT8183_RDMA0_SOUT_COLOR0),
};
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
......
drivers/soc/mediatek/mt8186-mmsys.h
+ 33
− 55
View file @ 7a6b5c34
......@@ -63,61 +63,39 @@
#define MT8186_MMSYS_SW0_RST_B 0x160
static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
MT8186_OVL0_MOUT_TO_RDMA0
},
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
MT8186_RDMA0_FROM_OVL0
},
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
MT8186_OVL0_GO_BLEND
},
{
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
MT8186_RDMA0_SOUT_TO_COLOR0
},
{
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0,
},
{
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0
},
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
MT8186_OVL0_2L_MOUT_TO_RDMA1
},
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
MT8186_RDMA1_FROM_OVL0_2L
},
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
MT8186_OVL0_2L_GO_BLEND
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
MT8186_RDMA1_MOUT_TO_DPI0_SEL
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
MT8186_DPI0_FROM_RDMA1
},
MMSYS_ROUTE(OVL0, RDMA0,
MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
MT8186_OVL0_MOUT_TO_RDMA0),
MMSYS_ROUTE(OVL0, RDMA0,
MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
MT8186_RDMA0_FROM_OVL0),
MMSYS_ROUTE(OVL0, RDMA0,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
MT8186_OVL0_GO_BLEND),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
MT8186_RDMA0_SOUT_TO_COLOR0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0),
MMSYS_ROUTE(OVL_2L0, RDMA1,
MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
MT8186_OVL0_2L_MOUT_TO_RDMA1),
MMSYS_ROUTE(OVL_2L0, RDMA1,
MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
MT8186_RDMA1_FROM_OVL0_2L),
MMSYS_ROUTE(OVL_2L0, RDMA1,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
MT8186_OVL0_2L_GO_BLEND),
MMSYS_ROUTE(RDMA1, DPI0,
MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
MT8186_RDMA1_MOUT_TO_DPI0_SEL),
MMSYS_ROUTE(RDMA1, DPI0,
MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
MT8186_DPI0_FROM_RDMA1),
};
#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */
drivers/soc/mediatek/mt8192-mmsys.h
+ 30
− 41
View file @ 7a6b5c34
......@@ -31,47 +31,36 @@
#define MT8192_DSI0_SEL_IN_DITHER0 0x1
static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
MT8192_OVL0_MOUT_EN_DISP_RDMA0
}, {
DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0
}, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
MT8192_RDMA0_SEL_IN_OVL0_2L
}, {
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
MT8192_RDMA0_SOUT_COLOR0
}, {
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
MT8192_CCORR0_SOUT_AAL0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
MT8192_DISP_OVL0_GO_BG
}, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
MT8192_DISP_OVL0_2L_GO_BLEND
}
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
MT8192_OVL0_MOUT_EN_DISP_RDMA0),
MMSYS_ROUTE(OVL_2L2, RDMA4,
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4),
MMSYS_ROUTE(DITHER0, DSI0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
MT8192_RDMA0_SEL_IN_OVL0_2L),
MMSYS_ROUTE(CCORR, AAL0,
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
MT8192_RDMA0_SOUT_COLOR0),
MMSYS_ROUTE(CCORR, AAL0,
MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
MT8192_CCORR0_SOUT_AAL0),
MMSYS_ROUTE(OVL0, OVL_2L0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
MT8192_DISP_OVL0_GO_BG),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
MT8192_DISP_OVL0_2L_GO_BLEND),
};
#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
drivers/soc/mediatek/mt8195-mmsys.h
+ 270
− 362
View file @ 7a6b5c34
This diff is collapsed.
drivers/soc/mediatek/mt8365-mmsys.h
+ 31
− 41
View file @ 7a6b5c34
......@@ -28,47 +28,37 @@
#define MT8365_DPI0_SEL_IN_RDMA1 0x0
static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0
}, {
DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0
},
MMSYS_ROUTE(OVL0, RDMA0,
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL),
MMSYS_ROUTE(OVL0, RDMA0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0),
MMSYS_ROUTE(COLOR0, CCORR,
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0),
MMSYS_ROUTE(RDMA1, DPI0,
MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK),
MMSYS_ROUTE(RDMA1, DPI0,
MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA1, DPI0,
MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0),
};
#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
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