wip

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>

arch/arm64/boot/dts/mediatek/mt8188.dtsi

@@ -3164,6 +3164,8 @@ vdosys0: syscon@1c01d000 {
 			#reset-cells = <1>;
 			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
 			mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
+			assigned-clocks = <&topckgen CLK_TOP_VPP>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
 		};
 
 		larb0: smi@1c022000 {
@@ -3215,6 +3217,8 @@ vdosys1: syscon@1c100000 {
 			#reset-cells = <1>;
 			mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
 			mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
+			assigned-clocks = <&topckgen CLK_TOP_VPP>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
 		};
 
 		mutex1: mutex@1c101000 {
@@ -3454,7 +3458,8 @@ ethdr0: ethdr@1c114000 {
 			      <0 0x1c11c000 0 0x1000>;
 			reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
 				    "vdo_be", "adl_ds";
-
+			assigned-clocks = <&topckgen CLK_TOP_ETHDR>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
 			clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
 				 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
 				 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,