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32 results

xstate.h

  • Yu-cheng Yu's avatar
    a65050c6
    x86/fpu: Revert ("x86/fpu: Disable AVX when eagerfpu is off") · a65050c6
    Yu-cheng Yu authored
    
    Leonid Shatz noticed that the SDM interpretation of the following
    recent commit:
    
      394db20c ("x86/fpu: Disable AVX when eagerfpu is off")
    
    ... is incorrect and that the original behavior of the FPU code was correct.
    
    Because AVX is not stated in CR0 TS bit description, it was mistakenly
    believed to be not supported for lazy context switch. This turns out
    to be false:
    
      Intel Software Developer's Manual Vol. 3A, Sec. 2.5 Control Registers:
    
       'TS Task Switched bit (bit 3 of CR0) -- Allows the saving of the x87 FPU/
        MMX/SSE/SSE2/SSE3/SSSE3/SSE4 context on a task switch to be delayed until
        an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction is actually executed
        by the new task.'
    
      Intel Software Developer's Manual Vol. 2A, Sec. 2.4 Instruction Exception
      Specification:
    
       'AVX instructions refer to exceptions by classes that include #NM
        "Device Not Available" exception for lazy context switch.'
    
    So revert the commit.
    
    Reported-by: default avatarLeonid Shatz <leonid.shatz@ravellosystems.com>
    Signed-off-by: default avatarYu-cheng Yu <yu-cheng.yu@intel.com>
    Cc: Andy Lutomirski <luto@kernel.org>
    Cc: Borislav Petkov <bp@suse.de>
    Cc: Dave Hansen <dave.hansen@linux.intel.com>
    Cc: Fenghua Yu <fenghua.yu@intel.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Ravi V. Shankar <ravi.v.shankar@intel.com>
    Cc: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Link: http://lkml.kernel.org/r/1457569734-3785-1-git-send-email-yu-cheng.yu@intel.com
    
    
    Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
    a65050c6
    History
    x86/fpu: Revert ("x86/fpu: Disable AVX when eagerfpu is off")
    Yu-cheng Yu authored
    
    Leonid Shatz noticed that the SDM interpretation of the following
    recent commit:
    
      394db20c ("x86/fpu: Disable AVX when eagerfpu is off")
    
    ... is incorrect and that the original behavior of the FPU code was correct.
    
    Because AVX is not stated in CR0 TS bit description, it was mistakenly
    believed to be not supported for lazy context switch. This turns out
    to be false:
    
      Intel Software Developer's Manual Vol. 3A, Sec. 2.5 Control Registers:
    
       'TS Task Switched bit (bit 3 of CR0) -- Allows the saving of the x87 FPU/
        MMX/SSE/SSE2/SSE3/SSSE3/SSE4 context on a task switch to be delayed until
        an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction is actually executed
        by the new task.'
    
      Intel Software Developer's Manual Vol. 2A, Sec. 2.4 Instruction Exception
      Specification:
    
       'AVX instructions refer to exceptions by classes that include #NM
        "Device Not Available" exception for lazy context switch.'
    
    So revert the commit.
    
    Reported-by: default avatarLeonid Shatz <leonid.shatz@ravellosystems.com>
    Signed-off-by: default avatarYu-cheng Yu <yu-cheng.yu@intel.com>
    Cc: Andy Lutomirski <luto@kernel.org>
    Cc: Borislav Petkov <bp@suse.de>
    Cc: Dave Hansen <dave.hansen@linux.intel.com>
    Cc: Fenghua Yu <fenghua.yu@intel.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Ravi V. Shankar <ravi.v.shankar@intel.com>
    Cc: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Link: http://lkml.kernel.org/r/1457569734-3785-1-git-send-email-yu-cheng.yu@intel.com
    
    
    Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>