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32 results

spi_imx.c

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  • spi_imx.c 45.47 KiB
    /*
     * drivers/spi/spi_imx.c
     *
     * Copyright (C) 2006 SWAPP
     *	Andrea Paterniani <a.paterniani@swapp-eng.it>
     *
     * Initial version inspired by:
     *	linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License as published by
     * the Free Software Foundation; either version 2 of the License, or
     * (at your option) any later version.
     *
     * This program is distributed in the hope that it will be useful,
     * but WITHOUT ANY WARRANTY; without even the implied warranty of
     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     * GNU General Public License for more details.
     */
    
    #include <linux/init.h>
    #include <linux/module.h>
    #include <linux/device.h>
    #include <linux/ioport.h>
    #include <linux/errno.h>
    #include <linux/interrupt.h>
    #include <linux/platform_device.h>
    #include <linux/dma-mapping.h>
    #include <linux/spi/spi.h>
    #include <linux/workqueue.h>
    #include <linux/delay.h>
    
    #include <asm/io.h>
    #include <asm/irq.h>
    #include <asm/hardware.h>
    #include <asm/delay.h>
    
    #include <asm/arch/hardware.h>
    #include <asm/arch/imx-dma.h>
    #include <asm/arch/spi_imx.h>
    
    /*-------------------------------------------------------------------------*/
    /* SPI Registers offsets from peripheral base address */
    #define SPI_RXDATA		(0x00)
    #define SPI_TXDATA		(0x04)
    #define SPI_CONTROL		(0x08)
    #define SPI_INT_STATUS		(0x0C)
    #define SPI_TEST		(0x10)
    #define SPI_PERIOD		(0x14)
    #define SPI_DMA			(0x18)
    #define SPI_RESET		(0x1C)
    
    /* SPI Control Register Bit Fields & Masks */
    #define SPI_CONTROL_BITCOUNT_MASK	(0xF)		/* Bit Count Mask */
    #define SPI_CONTROL_BITCOUNT(n)		(((n) - 1) & SPI_CONTROL_BITCOUNT_MASK)
    #define SPI_CONTROL_POL			(0x1 << 4)      /* Clock Polarity Mask */
    #define SPI_CONTROL_POL_ACT_HIGH	(0x0 << 4)      /* Active high pol. (0=idle) */
    #define SPI_CONTROL_POL_ACT_LOW		(0x1 << 4)      /* Active low pol. (1=idle) */
    #define SPI_CONTROL_PHA			(0x1 << 5)      /* Clock Phase Mask */
    #define SPI_CONTROL_PHA_0		(0x0 << 5)      /* Clock Phase 0 */
    #define SPI_CONTROL_PHA_1		(0x1 << 5)      /* Clock Phase 1 */
    #define SPI_CONTROL_SSCTL		(0x1 << 6)      /* /SS Waveform Select Mask */
    #define SPI_CONTROL_SSCTL_0		(0x0 << 6)      /* Master: /SS stays low between SPI burst
    							   Slave: RXFIFO advanced by BIT_COUNT */
    #define SPI_CONTROL_SSCTL_1		(0x1 << 6)      /* Master: /SS insert pulse between SPI burst
    							   Slave: RXFIFO advanced by /SS rising edge */
    #define SPI_CONTROL_SSPOL		(0x1 << 7)      /* /SS Polarity Select Mask */
    #define SPI_CONTROL_SSPOL_ACT_LOW	(0x0 << 7)      /* /SS Active low */
    #define SPI_CONTROL_SSPOL_ACT_HIGH	(0x1 << 7)      /* /SS Active high */
    #define SPI_CONTROL_XCH			(0x1 << 8)      /* Exchange */