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32 results

pgalloc.h

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    • Mikulas Patocka's avatar
      b37d1c18
      parisc: Use per-pagetable spinlock · b37d1c18
      Mikulas Patocka authored
      
      PA-RISC uses a global spinlock to protect pagetable updates in the TLB
      fault handlers. When multiple cores are taking TLB faults simultaneously,
      the cache line containing the spinlock becomes a bottleneck.
      
      This patch embeds the spinlock in the top level page directory, so that
      every process has its own lock. It improves performance by 30% when
      doing parallel compilations.
      
      At least on the N class systems, only one PxTLB inter processor
      broadcast can be active at any one time on the Merced bus. If a Merced
      bus is found, this patch serializes the TLB flushes with the
      pa_tlb_flush_lock spinlock.
      
      v1: Initial patch by Mikulas
      v2: Added Merced detection by Helge
      v3: Revised TLB serialization by Dave & Helge
      
      Signed-off-by: default avatarMikulas Patocka <mpatocka@redhat.com>
      Signed-off-by: default avatarJohn David Anglin <dave.anglin@bell.net>
      Signed-off-by: default avatarHelge Deller <deller@gmx.de>
      b37d1c18
      History
      parisc: Use per-pagetable spinlock
      Mikulas Patocka authored
      
      PA-RISC uses a global spinlock to protect pagetable updates in the TLB
      fault handlers. When multiple cores are taking TLB faults simultaneously,
      the cache line containing the spinlock becomes a bottleneck.
      
      This patch embeds the spinlock in the top level page directory, so that
      every process has its own lock. It improves performance by 30% when
      doing parallel compilations.
      
      At least on the N class systems, only one PxTLB inter processor
      broadcast can be active at any one time on the Merced bus. If a Merced
      bus is found, this patch serializes the TLB flushes with the
      pa_tlb_flush_lock spinlock.
      
      v1: Initial patch by Mikulas
      v2: Added Merced detection by Helge
      v3: Revised TLB serialization by Dave & Helge
      
      Signed-off-by: default avatarMikulas Patocka <mpatocka@redhat.com>
      Signed-off-by: default avatarJohn David Anglin <dave.anglin@bell.net>
      Signed-off-by: default avatarHelge Deller <deller@gmx.de>
    intel-gtt.h 941 B
    /* Common header for intel-gtt.ko and i915.ko */
    
    #ifndef _DRM_INTEL_GTT_H
    #define	_DRM_INTEL_GTT_H
    
    void intel_gtt_get(u64 *gtt_total, size_t *stolen_size,
    		   phys_addr_t *mappable_base, u64 *mappable_end);
    
    int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
    		     struct agp_bridge_data *bridge);
    void intel_gmch_remove(void);
    
    bool intel_enable_gtt(void);
    
    void intel_gtt_chipset_flush(void);
    void intel_gtt_insert_page(dma_addr_t addr,
    			   unsigned int pg,
    			   unsigned int flags);
    void intel_gtt_insert_sg_entries(struct sg_table *st,
    				 unsigned int pg_start,
    				 unsigned int flags);
    void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
    
    /* Special gtt memory types */
    #define AGP_DCACHE_MEMORY	1
    #define AGP_PHYS_MEMORY		2
    
    /* flag for GFDT type */
    #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
    
    #ifdef CONFIG_INTEL_IOMMU
    extern int intel_iommu_gfx_mapped;
    #endif
    
    #endif