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net/mlx5: Accel, Add TLS tx offload interface
Add routines for manipulating TLS TX offload contexts. In Innova TLS, TLS contexts are added or deleted via a command message over the SBU connection. The HW then sends a response message over the same connection. Add implementation for Innova TLS (FPGA-based) hardware. These routines will be used by the TLS offload support in a later patch mlx5/accel is a middle acceleration layer to allow mlx5e and other ULPs to work directly with mlx5_core rather than Innova FPGA or other mlx5 acceleration providers. In the future, when IPSec/TLS or any other acceleration gets integrated into ConnectX chip, mlx5/accel layer will provide the integrated acceleration, rather than the Innova one. Signed-off-by:Ilya Lesokhin <ilyal@mellanox.com> Signed-off-by:
Boris Pismenny <borisp@mellanox.com> Acked-by:
Saeed Mahameed <saeedm@mellanox.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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- drivers/net/ethernet/mellanox/mlx5/core/Makefile 2 additions, 2 deletionsdrivers/net/ethernet/mellanox/mlx5/core/Makefile
- drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c 71 additions, 0 deletionsdrivers/net/ethernet/mellanox/mlx5/core/accel/tls.c
- drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h 86 additions, 0 deletionsdrivers/net/ethernet/mellanox/mlx5/core/accel/tls.h
- drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h 1 addition, 0 deletionsdrivers/net/ethernet/mellanox/mlx5/core/fpga/core.h
- drivers/net/ethernet/mellanox/mlx5/core/fpga/tls.c 562 additions, 0 deletionsdrivers/net/ethernet/mellanox/mlx5/core/fpga/tls.c
- drivers/net/ethernet/mellanox/mlx5/core/fpga/tls.h 68 additions, 0 deletionsdrivers/net/ethernet/mellanox/mlx5/core/fpga/tls.h
- drivers/net/ethernet/mellanox/mlx5/core/main.c 11 additions, 0 deletionsdrivers/net/ethernet/mellanox/mlx5/core/main.c
- include/linux/mlx5/mlx5_ifc.h 0 additions, 16 deletionsinclude/linux/mlx5/mlx5_ifc.h
- include/linux/mlx5/mlx5_ifc_fpga.h 77 additions, 0 deletionsinclude/linux/mlx5/mlx5_ifc_fpga.h
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