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Commit 22c58fd7 authored by Linus Torvalds's avatar Linus Torvalds
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Pull ARM SoC platform updates from Olof Johansson:
 "SoC updates, mostly refactorings and cleanups of old legacy platforms.

  Major themes this release:

   - Conversion of ixp4xx to a modern platform (drivers, DT, bindings)

   - Moving some of the ep93xx headers around to get it closer to
     multiplatform enabled.

   - Cleanups of Davinci

  This also contains a few patches that were queued up as fixes before
  5.1 but I didn't get sent in before release"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (123 commits)
  ARM: debug-ll: add default address for digicolor
  ARM: u300: regulator: add MODULE_LICENSE()
  ARM: ep93xx: move private headers out of mach/*
  ARM: ep93xx: move pinctrl interfaces into include/linux/soc
  ARM: ep93xx: keypad: stop using mach/platform.h
  ARM: ep93xx: move network platform data to separate header
  ARM: stm32: add AMBA support for stm32 family
  MAINTAINERS: update arch/arm/mach-davinci
  ARM: rockchip: add missing of_node_put in rockchip_smp_prepare_pmu
  ARM: dts: Add queue manager and NPE to the IXP4xx DTSI
  soc: ixp4xx: qmgr: Add DT probe code
  soc: ixp4xx: qmgr: Add DT bindings for IXP4xx qmgr
  soc: ixp4xx: npe: Add DT probe code
  soc: ixp4xx: Add DT bindings for IXP4xx NPE
  soc: ixp4xx: qmgr: Pass resources
  soc: ixp4xx: Remove unused functions
  soc: ixp4xx: Uninline several functions
  soc: ixp4xx: npe: Pass addresses as resources
  ARM: ixp4xx: Turn the QMGR into a platform device
  ARM: ixp4xx: Turn the NPE into a platform device
  ...
parents a455eda3 7a0c4c17
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx Device Tree Bindings
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
compatible:
oneOf:
- items:
- enum:
- linksys,nslu2
- const: intel,ixp42x
- items:
- enum:
- gateworks,gw2358
- const: intel,ixp43x
...@@ -94,6 +94,8 @@ Optional properties: ...@@ -94,6 +94,8 @@ Optional properties:
- ti,no-idle-on-init interconnect target module should not be idled at init - ti,no-idle-on-init interconnect target module should not be idled at init
- ti,no-idle interconnect target module should not be idled
Example: Single instance of MUSB controller on omap4 using interconnect ranges Example: Single instance of MUSB controller on omap4 using interconnect ranges
using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
...@@ -131,6 +133,6 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): ...@@ -131,6 +133,6 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
}; };
}; };
Note that other SoCs, such as am335x can have multipe child devices. On am335x Note that other SoCs, such as am335x can have multiple child devices. On am335x
there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
instance as children of a single interconnet target module. instance as children of a single interconnect target module.
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx Network Processing Engine
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
processor that can load a firmware to perform offloading of networking
and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
on the IXP4xx platform. All IXP4xx platforms have three NPEs at
consecutive memory locations. They are all included in the same
device node since they are not independent of each other.
properties:
compatible:
oneOf:
- items:
- const: intel,ixp4xx-network-processing-engine
reg:
minItems: 3
maxItems: 3
items:
- description: NPE0 register range
- description: NPE1 register range
- description: NPE2 register range
required:
- compatible
- reg
examples:
- |
npe@c8006000 {
compatible = "intel,ixp4xx-network-processing-engine";
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt/intel-ixp4xx-interrupt.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx XScale Networking Processors Interrupt Controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
This interrupt controller is found in the Intel IXP4xx processors.
Some processors have 32 interrupts, some have up to 64 interrupts.
The exact number of interrupts is determined from the compatible
string.
The distinct IXP4xx families with different interrupt controller
variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four
families were the only ones to reach the developer and consumer
market.
properties:
compatible:
items:
- enum:
- intel,ixp42x-interrupt
- intel,ixp43x-interrupt
- intel,ixp45x-interrupt
- intel,ixp46x-interrupt
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
examples:
- |
intcon: interrupt-controller@c8003000 {
compatible = "intel,ixp43x-interrupt";
reg = <0xc8003000 0x100>;
interrupt-controller;
#interrupt-cells = <2>;
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/misc/intel-ixp4xx-ahb-queue-manager.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx AHB Queue Manager
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
The IXP4xx AHB Queue Manager maintains queues as circular buffers in
an 8KB embedded SRAM along with hardware pointers. It is used by both
the XScale processor and the NPEs (Network Processing Units) in the
IXP4xx for accelerating queues, especially for networking. Clients pick
queues from the queue manager with foo-queue = <&qmgr N> where the
&qmgr is a phandle to the queue manager and N is the queue resource
number. The queue resources available and their specific purpose
on a certain IXP4xx system will vary.
properties:
compatible:
items:
- const: intel,ixp4xx-ahb-queue-manager
reg:
maxItems: 1
interrupts:
items:
- description: Interrupt for queues 0-31
- description: Interrupt for queues 32-63
required:
- compatible
- reg
- interrupts
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
qmgr: queue-manager@60000000 {
compatible = "intel,ixp4xx-ahb-queue-manager";
reg = <0x60000000 0x4000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/timer/intel-ixp4xx-timer.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx XScale Networking Processors Timers
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: This timer is found in the Intel IXP4xx processors.
properties:
compatible:
items:
- const: intel,ixp4xx-timer
reg:
description: Should contain registers location and length
interrupts:
minItems: 1
maxItems: 2
items:
- description: Timer 1 interrupt
- description: Timer 2 interrupt
required:
- compatible
- reg
- interrupts
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
timer@c8005000 {
compatible = "intel,ixp4xx-timer";
reg = <0xc8005000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
...@@ -1733,11 +1733,21 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) ...@@ -1733,11 +1733,21 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained S: Maintained
ARM/INTEL IXP4XX ARM ARCHITECTURE ARM/INTEL IXP4XX ARM ARCHITECTURE
M: Linus Walleij <linusw@kernel.org>
M: Imre Kaloz <kaloz@openwrt.org> M: Imre Kaloz <kaloz@openwrt.org>
M: Krzysztof Halasa <khalasa@piap.pl> M: Krzysztof Halasa <khalasa@piap.pl>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
F: arch/arm/mach-ixp4xx/ F: arch/arm/mach-ixp4xx/
F: drivers/clocksource/timer-ixp4xx.c
F: drivers/gpio/gpio-ixp4xx.c
F: drivers/irqchip/irq-ixp4xx.c
F: include/linux/irqchip/irq-ixp4xx.h
F: include/linux/platform_data/timer-ixp4xx.h
ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
M: Jonathan Cameron <jic23@cam.ac.uk> M: Jonathan Cameron <jic23@cam.ac.uk>
...@@ -2238,6 +2248,7 @@ F: arch/arm/mach-socfpga/ ...@@ -2238,6 +2248,7 @@ F: arch/arm/mach-socfpga/
F: arch/arm/boot/dts/socfpga* F: arch/arm/boot/dts/socfpga*
F: arch/arm/configs/socfpga_defconfig F: arch/arm/configs/socfpga_defconfig
F: arch/arm64/boot/dts/altera/ F: arch/arm64/boot/dts/altera/
F: arch/arm64/boot/dts/intel/
W: http://www.rocketboards.org W: http://www.rocketboards.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
...@@ -7990,10 +8001,10 @@ F: Documentation/media/v4l-drivers/ipu3.rst ...@@ -7990,10 +8001,10 @@ F: Documentation/media/v4l-drivers/ipu3.rst
INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT
M: Krzysztof Halasa <khalasa@piap.pl> M: Krzysztof Halasa <khalasa@piap.pl>
S: Maintained S: Maintained
F: arch/arm/mach-ixp4xx/include/mach/qmgr.h F: include/linux/soc/ixp4xx/qmgr.h
F: arch/arm/mach-ixp4xx/include/mach/npe.h F: include/linux/soc/ixp4xx/npe.h
F: arch/arm/mach-ixp4xx/ixp4xx_qmgr.c F: drivers/soc/ixp4xx/ixp4xx-qmgr.c
F: arch/arm/mach-ixp4xx/ixp4xx_npe.c F: drivers/soc/ixp4xx/ixp4xx-npe.c
F: drivers/net/ethernet/xscale/ixp4xx_eth.c F: drivers/net/ethernet/xscale/ixp4xx_eth.c
F: drivers/net/wan/ixp4xx_hss.c F: drivers/net/wan/ixp4xx_hss.c
...@@ -15654,7 +15665,7 @@ F: include/linux/clk/ti.h ...@@ -15654,7 +15665,7 @@ F: include/linux/clk/ti.h
TI DAVINCI MACHINE SUPPORT TI DAVINCI MACHINE SUPPORT
M: Sekhar Nori <nsekhar@ti.com> M: Sekhar Nori <nsekhar@ti.com>
M: Kevin Hilman <khilman@kernel.org> R: Bartosz Golaszewski <bgolaszewski@baylibre.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci.git
S: Supported S: Supported
......
...@@ -426,12 +426,15 @@ config ARCH_IXP4XX ...@@ -426,12 +426,15 @@ config ARCH_IXP4XX
depends on MMU depends on MMU
select ARCH_HAS_DMA_SET_COHERENT_MASK select ARCH_HAS_DMA_SET_COHERENT_MASK
select ARCH_SUPPORTS_BIG_ENDIAN select ARCH_SUPPORTS_BIG_ENDIAN
select CLKSRC_MMIO
select CPU_XSCALE select CPU_XSCALE
select DMABOUNCE if PCI select DMABOUNCE if PCI
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_MULTI_HANDLER
select GPIO_IXP4XX
select GPIOLIB select GPIOLIB
select HAVE_PCI select HAVE_PCI
select IXP4XX_IRQ
select IXP4XX_TIMER
select NEED_MACH_IO_H select NEED_MACH_IO_H
select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_DESC
select USB_EHCI_BIG_ENDIAN_MMIO select USB_EHCI_BIG_ENDIAN_MMIO
...@@ -897,8 +900,6 @@ config PLAT_PXA ...@@ -897,8 +900,6 @@ config PLAT_PXA
config PLAT_VERSATILE config PLAT_VERSATILE
bool bool
source "arch/arm/firmware/Kconfig"
source "arch/arm/mm/Kconfig" source "arch/arm/mm/Kconfig"
config IWMMXT config IWMMXT
......
...@@ -1676,6 +1676,7 @@ config DEBUG_UART_PHYS ...@@ -1676,6 +1676,7 @@ config DEBUG_UART_PHYS
default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1 default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1
default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4 default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
default 0xe8008000 if DEBUG_R7S72100_SCIF2 default 0xe8008000 if DEBUG_R7S72100_SCIF2
default 0xf0000000 if DEBUG_DIGICOLOR_UA0
default 0xf0000be0 if ARCH_EBSA110 default 0xf0000be0 if ARCH_EBSA110
default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
default 0xf1012100 if DEBUG_MVEBU_UART1_ALTERNATE default 0xf1012100 if DEBUG_MVEBU_UART1_ALTERNATE
...@@ -1727,6 +1728,7 @@ config DEBUG_UART_VIRT ...@@ -1727,6 +1728,7 @@ config DEBUG_UART_VIRT
default 0xe0010fe0 if ARCH_RPC default 0xe0010fe0 if ARCH_RPC
default 0xf0000be0 if ARCH_EBSA110 default 0xf0000be0 if ARCH_EBSA110
default 0xf0010000 if DEBUG_ASM9260_UART default 0xf0010000 if DEBUG_ASM9260_UART
default 0xf0100000 if DEBUG_DIGICOLOR_UA0
default 0xf01fb000 if DEBUG_NOMADIK_UART default 0xf01fb000 if DEBUG_NOMADIK_UART
default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836 default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836
default 0xf1000300 if DEBUG_BCM_5301X default 0xf1000300 if DEBUG_BCM_5301X
......
...@@ -290,7 +290,6 @@ core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ ...@@ -290,7 +290,6 @@ core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
core-y += arch/arm/probes/ core-y += arch/arm/probes/
core-y += arch/arm/net/ core-y += arch/arm/net/
core-y += arch/arm/crypto/ core-y += arch/arm/crypto/
core-y += arch/arm/firmware/
core-y += $(machdirs) $(platdirs) core-y += $(machdirs) $(platdirs)
drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
......
...@@ -229,6 +229,9 @@ dtb-$(CONFIG_ARCH_HIX5HD2) += \ ...@@ -229,6 +229,9 @@ dtb-$(CONFIG_ARCH_HIX5HD2) += \
dtb-$(CONFIG_ARCH_INTEGRATOR) += \ dtb-$(CONFIG_ARCH_INTEGRATOR) += \
integratorap.dtb \ integratorap.dtb \
integratorcp.dtb integratorcp.dtb
dtb-$(CONFIG_ARCH_IXP4XX) += \
intel-ixp42x-linksys-nslu2.dtb \
intel-ixp43x-gateworks-gw2358.dtb
dtb-$(CONFIG_ARCH_KEYSTONE) += \ dtb-$(CONFIG_ARCH_KEYSTONE) += \
keystone-k2hk-evm.dtb \ keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \ keystone-k2l-evm.dtb \
......
...@@ -88,6 +88,7 @@ ...@@ -88,6 +88,7 @@
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high; enable-active-high;
}; };
...@@ -99,6 +100,7 @@ ...@@ -99,6 +100,7 @@
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high; enable-active-high;
regulator-always-on; regulator-always-on;
}; };
...@@ -216,7 +218,7 @@ ...@@ -216,7 +218,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-duration = <10>; phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_enet>; phy-supply = <&reg_enet>;
......
...@@ -92,7 +92,7 @@ ...@@ -92,7 +92,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
......
...@@ -171,7 +171,7 @@ ...@@ -171,7 +171,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
status = "okay"; status = "okay";
}; };
......
...@@ -110,7 +110,7 @@ ...@@ -110,7 +110,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -98,7 +98,7 @@ ...@@ -98,7 +98,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -51,7 +51,7 @@ ...@@ -51,7 +51,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-duration = <10>; phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
......
...@@ -292,7 +292,7 @@ ...@@ -292,7 +292,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present; fsl,err006687-workaround-present;
......
...@@ -202,7 +202,7 @@ ...@@ -202,7 +202,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -53,7 +53,7 @@ ...@@ -53,7 +53,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-duration = <2>; phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
......
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