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  1. Apr 28, 2008
  2. Mar 12, 2008
  3. Dec 14, 2007
  4. Nov 15, 2007
    • Ralf Baechle's avatar
      [MIPS] Fix shadow register support. · f6771dbb
      Ralf Baechle authored
      
      Shadow register support would not possibly have worked on multicore
      systems.  The support code for it was also depending not on MIPS R2 but
      VSMP or SMTC kernels even though it makes perfect sense with UP kernels.
      
      SR sets are a scarce resource and the expected usage pattern is that
      users actually hardcode the register set numbers in their code.  So fix
      the allocator by ditching it.  Move the remaining CPU probe bits into
      the generic CPU probe.
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      f6771dbb
  5. Oct 19, 2007
  6. Oct 18, 2007
  7. Oct 17, 2007
    • Maciej W. Rozycki's avatar
      [MIPS] SYNC emulation for MIPS I processors · 60b0d655
      Maciej W. Rozycki authored
      
      Userland, including the C library and the dynamic linker, is keen to use
      the SYNC instruction, even for "generic" MIPS I binaries these days.
      Which makes it less than useful on MIPS I processors.
      
      This change adds the emulation, but as our do_ri() infrastructure was not
      really prepared to take yet another instruction, I have rewritten it and
      its callees slightly as follows.
      
      Now there is only a single place a possible signal is thrown from.  The
      place is at the end of do_ri().  The instruction word is fetched in
      do_ri() and passed down to handlers.  The handlers are called in sequence
      and return a result that lets the caller decide upon further processing.
      If the result is positive, then the handler has picked the instruction,
      but a signal should be thrown and the result is the signal number.  If the
      result is zero, then the handler has successfully simulated the
      instruction.  If the result is negative, then the handler did not handle
      the instruction; to make it more obvious the calls do not follow the usual
      0/-Exxx result convention they now return -1 instead of -EFAULT.
      
      The calculation of the return EPC is now at the beginning.  The reason is
      it is easier to handle it there as emulation callees may modify a register
      and an instruction may be located in delay slot of a branch whose result
      depends on the register.  It has to be undone if a signal is to be raised,
      but it is not a problem as this is the slow-path case, and both actions
      are done in single places now rather than the former being scattered
      through emulation handlers.
      
      The part of do_cpu() being covered follows the changes to do_ri().
      
      Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      
      ---
      60b0d655
  8. Oct 16, 2007
    • Ralf Baechle's avatar
      [MIPS] IP22: Fix warning. · eae23f2c
      Ralf Baechle authored
      
        CC      arch/mips/sgi-ip22/ip22-berr.o
      arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt':
      arch/mips/sgi-ip22/ip22-berr.c:100: warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      eae23f2c
  9. Oct 11, 2007
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  17. Jun 20, 2007
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  20. May 11, 2007
  21. May 08, 2007
  22. Apr 20, 2007
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