[WIP] drm/mediatek: ovl: Always decode AFBC data with YUV transform

Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

@@ -37,6 +37,7 @@
 #define DISP_REG_OVL_OFFSET(n)			(0x003c + 0x20 * (n))
 #define DISP_REG_OVL_PITCH_MSB(n)		(0x0040 + 0x20 * (n))
 #define OVL_PITCH_MSB_2ND_SUBBUF			BIT(16)
+#define OVL_PITCH_MSB_YUV_TRANS				BIT(20)
 #define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20 * (n))
 #define OVL_CONST_BLEND					BIT(28)
 #define DISP_REG_OVL_CLIP(n)			(0x004C + 0x20 * (n))
@@ -478,7 +479,7 @@ static void mtk_ovl_afbc_layer_config(struct mtk_disp_ovl *ovl,
 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,
 				      DISP_REG_OVL_HDR_ADDR(ovl, idx));
 		mtk_ddp_write_relaxed(cmdq_pkt,
-				      OVL_PITCH_MSB_2ND_SUBBUF | pitch_msb,
+				      OVL_PITCH_MSB_YUV_TRANS | OVL_PITCH_MSB_2ND_SUBBUF | pitch_msb,
 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,
 				      DISP_REG_OVL_HDR_PITCH(ovl, idx));