- Sep 06, 2022
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
Now that the clock sharing for i2s ports can be configured from the sound machine driver, remove the logic that was used to parse the properties from the devicetree. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
i2s0 and i2s1 are paired input/output connected to the same codec and should share the same clock. Likewise for i2s2 and i2s3. Set the clock sharing for each pair during the codec's initialization. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
Add a new function to configure the shared clock between two i2s ports, and export it. This will allow the clock sharing to be set from the machine driver instead of the devicetree. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
The i2sN-share properties were never documented in the dt-binding and thus shouldn't be used. Now that the ASoC machine drivers are setting the I2S clock sharing internally, these properties are no longer needed, so remove them. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
Now that the clock sharing for i2s ports can be configured from the sound machine driver, remove the logic that was used to parse the properties from the devicetree. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
i2s0 and i2s5 are paired input/output connected to the same codec and should share the same clock. Likewise for i2s2 and i2s3. Set the clock sharing for each pair during the DAI initialization. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
Add a new function to configure the shared clock between two i2s ports, and export it. This will allow the clock sharing to be set from the machine driver instead of the devicetree. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
Now that the clock sharing for i2s ports can be configured from the sound machine driver, remove the logic that was used to parse the properties from the devicetree. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
Both i2s8 and i2s9 are connected to the rt5682 codec and should share the same clock to work in a full-duplex manner. Set the clock sharing during the initialization for rt5682. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
Add a new function to configure the shared clock between two i2s ports, and export it. This will allow the clock sharing to be set from the machine driver instead of the devicetree. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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- Sep 02, 2022
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Nícolas F. R. A. Prado authored
TODO: maybe add the others as well
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Nícolas F. R. A. Prado authored
Gets rid of a dtbs_check warning. Encoder clocks are: mt8173 CLK_TOP_VENC_SEL mt8183 CLK_VENC_VENC mt8192 CLK_VENC_SET1_VENC Clock name should be more generic.
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Nícolas F. R. A. Prado authored
Add 'if' blocks to prevent bias-disable, bias-pull-up and bias-pull-down to be used together, since they're mutually exclusive. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
Add a new 'if' block to validate that drive-strength and drive-strength-microamp aren't used together, since they're mutually exclusive. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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Add the callback function when the driver receives state changes of the Type-C port. The callback function configures the crosspoint switch of the anx7625 bridge chip, which can change the output pins of the signals according to the port state. Signed-off-by:
Pin-Yen Lin <treapking@chromium.org> Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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When the DT node has "switches" available, register a Type-C mode-switch for each listed "switch". This allows the driver to receive state information about what operating mode a Type-C port and its connected peripherals are in, as well as status information (like VDOs) related to that state. The callback function is currently a stub, but subsequent patches will implement the required functionality. Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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Parse the "switches" node, if available, and count and store the number of Type-C switches within it. Since we currently don't do anything with this info, no functional changes are expected from this change. This patch sets a foundation for the actual registering of Type-C switches with the Type-C connector class framework. Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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Analogix 7625 can be used in systems to switch USB Type-C DisplayPort alternate mode lane traffic between 2 Type-C ports. Update the binding to accommodate this usage by introducing a switch property. Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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Introduce a binding which represents a component that can control the routing of USB Type-C data lines as well as address data line orientation (based on CC lines' orientation). Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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Nícolas F. R. A. Prado authored
Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
It will rely on mtk regulator coupler driver instead.
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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This is a clock-controller binding, so it needs #clock-cells, or it would be of no use: add that to the list of required properties. Fixes: 4a803990 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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There's no need for 'items' when there's only one item. Fixes: 4a803990 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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This is a clock-controller binding, so it needs #clock-cells, or it would be of no use: add that to the list of required properties. Fixes: 34d3ed3b ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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There's no need for 'items' when there's only one item; while at it, also fix formatting by adding a blank line before specifying 'reg'. Fixes: 34d3ed3b ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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This is a clock-controller binding, so it needs #clock-cells, or it would be of no use: add that to the list of required properties. Fixes: f113a51a ("dt-bindings: ARM: MediaTek: Add new document bindings of MT8186 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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There's no need for 'items' when there's only one item; while at it, also fix formatting by adding a blank line before specifying 'reg'. Fixes: f113a51a ("dt-bindings: ARM: MediaTek: Add new document bindings of MT8186 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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Add a phandle to the MT8192_POWER_DOMAIN_MFG1 power domain and assign the GPU VSRAM supply to this in mt8192-asurada: this allows to keep the sram powered up while the GPU is used. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Add coupling for these regulators, as VSRAM_OTHER is used to power the GPU SRAM, and they have a strict voltage output relation to satisfy in order to ensure GPU stable operation. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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The mfg_ref_sel clock is a mux used to switch between different "safe" (and slower) clock sources for the GPU: this is used during MFGPLL reconfiguration and eventually during idling at very low frequencies. This clock getting turned off means that the GPU will occasionally be unclocked, producing obvious consequences such as system crash or unpredictable behavior: assigning it to the top level MFG power domain will make sure that this stays on at all times during any operation on the MFG domain (only GPU-related transactions). Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Following the changes that were done for mt8183, add a clock notifier for the GPU PLL selector mux: this allows safe clock rate changes by temporarily reparenting the GPU to a safe clock (clk26m) while the MFGPLL is reprogrammed and stabilizes. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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