- Sep 02, 2022
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Nícolas F. R. A. Prado authored
TODO: maybe add the others as well
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Nícolas F. R. A. Prado authored
Gets rid of a dtbs_check warning. Encoder clocks are: mt8173 CLK_TOP_VENC_SEL mt8183 CLK_VENC_VENC mt8192 CLK_VENC_SET1_VENC Clock name should be more generic.
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Nícolas F. R. A. Prado authored
Add 'if' blocks to prevent bias-disable, bias-pull-up and bias-pull-down to be used together, since they're mutually exclusive. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
Add a new 'if' block to validate that drive-strength and drive-strength-microamp aren't used together, since they're mutually exclusive. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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Add the callback function when the driver receives state changes of the Type-C port. The callback function configures the crosspoint switch of the anx7625 bridge chip, which can change the output pins of the signals according to the port state. Signed-off-by:
Pin-Yen Lin <treapking@chromium.org> Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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When the DT node has "switches" available, register a Type-C mode-switch for each listed "switch". This allows the driver to receive state information about what operating mode a Type-C port and its connected peripherals are in, as well as status information (like VDOs) related to that state. The callback function is currently a stub, but subsequent patches will implement the required functionality. Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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Parse the "switches" node, if available, and count and store the number of Type-C switches within it. Since we currently don't do anything with this info, no functional changes are expected from this change. This patch sets a foundation for the actual registering of Type-C switches with the Type-C connector class framework. Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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Analogix 7625 can be used in systems to switch USB Type-C DisplayPort alternate mode lane traffic between 2 Type-C ports. Update the binding to accommodate this usage by introducing a switch property. Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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Introduce a binding which represents a component that can control the routing of USB Type-C data lines as well as address data line orientation (based on CC lines' orientation). Signed-off-by:
Prashant Malani <pmalani@chromium.org>
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Nícolas F. R. A. Prado authored
Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com>
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
It will rely on mtk regulator coupler driver instead.
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Nícolas F. R. A. Prado authored
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Nícolas F. R. A. Prado authored
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This is a clock-controller binding, so it needs #clock-cells, or it would be of no use: add that to the list of required properties. Fixes: 4a803990 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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There's no need for 'items' when there's only one item. Fixes: 4a803990 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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This is a clock-controller binding, so it needs #clock-cells, or it would be of no use: add that to the list of required properties. Fixes: 34d3ed3b ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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There's no need for 'items' when there's only one item; while at it, also fix formatting by adding a blank line before specifying 'reg'. Fixes: 34d3ed3b ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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This is a clock-controller binding, so it needs #clock-cells, or it would be of no use: add that to the list of required properties. Fixes: f113a51a ("dt-bindings: ARM: MediaTek: Add new document bindings of MT8186 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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There's no need for 'items' when there's only one item; while at it, also fix formatting by adding a blank line before specifying 'reg'. Fixes: f113a51a ("dt-bindings: ARM: MediaTek: Add new document bindings of MT8186 clock") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com>
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Add a phandle to the MT8192_POWER_DOMAIN_MFG1 power domain and assign the GPU VSRAM supply to this in mt8192-asurada: this allows to keep the sram powered up while the GPU is used. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Add coupling for these regulators, as VSRAM_OTHER is used to power the GPU SRAM, and they have a strict voltage output relation to satisfy in order to ensure GPU stable operation. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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The mfg_ref_sel clock is a mux used to switch between different "safe" (and slower) clock sources for the GPU: this is used during MFGPLL reconfiguration and eventually during idling at very low frequencies. This clock getting turned off means that the GPU will occasionally be unclocked, producing obvious consequences such as system crash or unpredictable behavior: assigning it to the top level MFG power domain will make sure that this stays on at all times during any operation on the MFG domain (only GPU-related transactions). Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Following the changes that were done for mt8183, add a clock notifier for the GPU PLL selector mux: this allows safe clock rate changes by temporarily reparenting the GPU to a safe clock (clk26m) while the MFGPLL is reprogrammed and stabilizes. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Following what was done on MT8183 and MT8195, also propagate the rate changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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This driver currently deals with GPU-SRAM regulator coupling, ensuring that the SRAM voltage is always between a specific range of distance to the GPU voltage, depending on the SoC, necessary in order to achieve system stability across the full range of supported GPU frequencies. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Add the CLK_IS_CRITICAL flag to top_mfg_core_tmp as this clock is used for safe clock switching and GPU idling. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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These PLLs are conflicting with GPU rates that can be generated by the GPU-dedicated MFGPLL and would require a special clock handler to be used, for very little and ignorable power consumption benefits. Also, we're in any case unable to set the rate of these PLLs to something else that is sensible for this task, so simply drop them: this will make the GPU to be clocked exclusively from MFGPLL for "fast" rates, while still achieving the right "safe" rate during PLL frequency locking. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Following the changes done to MT8183, register a similar notifier for MT8195 as well, allowing safe clockrate updates for the MFGPLL. Signed-off-by:
AngeloGIoacchino Del Regno <angelogioacchino.delregno@collabora.com>
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This clock was being registered as clk-composite through the helpers for the same in the MediaTek clock APIs but, in reality, this isn't a composite clock. Appropriately register this clock with devm_clk_hw_register_mux(). No functional changes. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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The MFG_BG3D is a gate to enable/disable clock output to the GPU, but the actual output is decided by multiple muxes; in particular: mfg_ck_fast_ref muxes between "slow" (top_mfg_core_tmp) and "fast" (MFGPLL) clock, while top_mfg_core_tmp muxes between the 26MHz clock and various system PLLs. This also implies that "top_mfg_core_tmp" is a parent of the "mfg_ck_fast_ref" mux (and not vice-versa), so reparent the MFG_BG3D gate to the latter and add the CLK_SET_RATE_PARENT flag to it: this way we ensure propagating rate changes that are requested on MFG_BG3D along its entire clock tree. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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When the MFG PLL clock, which is upstream of the MFG clock, is changed, the downstream clock and consumers need to be switched away from the PLL over to a stable clock to avoid glitches. This is done through the use of the newly added clk mux notifier. The notifier is set on the mux itself instead of the upstream PLL, but in practice this works, as the rate change notifitcations are propogated throughout the sub-tree hanging off the PLL. Just before rate changes, the MFG mux is temporarily and transparently switched to the 26 MHz main crystal. After the rate change, the mux is switched back. Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> [Angelo: Rebased to assign clk_ops in mtk_mux_nb] Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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With device frequency scaling, the mux clock that (indirectly) feeds the device selects between a dedicated PLL, and some other stable clocks. When a clk rate change is requested, the (normally) upstream PLL is reconfigured. It's possible for the clock output of the PLL to become unstable during this process. To avoid causing the device to glitch, the mux should temporarily be switched over to another "stable" clock during the PLL rate change. This is done with clk notifiers. This patch adds common functions for notifiers to temporarily and transparently reparent mux clocks. This was loosely based on commit 8adfb086 ("clk: sunxi-ng: mux: Add clk notifier functions"). Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> [Angelo: Changed mtk_mux_nb hold a pointer to clk_ops instead of mtk_mux] Co-Developed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its rate change requests to its parent, so that DVFS for the GPU can work properly. Fixes: acddfc2c ("clk: mediatek: Add MT8183 clock support") Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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The actual clock feeding into the Mali GPU on the MT8183 is from the clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN block, which itself is simply a pass-through placeholder for the MFGPLL in the APMIXEDSYS block. Fix the hardware description with the correct clock reference. Fixes: a8168ceb ("arm64: dts: mt8183: Add node for the Mali GPU") Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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