• Andrzej Hajda's avatar
    i2c: exynos5: rework HSI2C_MASTER_ST_LOSE state handling · 939c5a46
    Andrzej Hajda authored
    HSI2C_MASTER_ST_LOSE state is not documented properly, extensive tests
    show that hardware is usually able to recover from this state without
    interrupting the transfer. Moreover documentation says that
    such state can be caused by slave clock stretching, and should not be
    treated as an error during transaction. The only place it indicates
    an error is just before starting transaction. In such case bus recovery
    procedure should be performed - master should pulse SCL line nine times
    and then send STOP condition, it can be repeated until SDA goes high.
    The procedure can be performed using manual commands HSI2C_CMD_READ_DATA
    Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
    Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
i2c-exynos5.c 23.6 KB