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    drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset · 101b506a
    Michel Thierry authored
    There are some allocations that must be only referenced by 32-bit
    offsets. To limit the chances of having the first 4GB already full,
    objects not requiring this workaround use DRM_MM_SEARCH_BELOW/
    DRM_MM_CREATE_TOP flags
    
    In specific, any resource used with flat/heapless (0x00000000-0xfffff000)
    General State Heap (GSH) or Instruction State Heap (ISH) must be in a
    32-bit range, because the General State Offset and Instruction State
    Offset are limited to 32-bits.
    
    Objects must have EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag to indicate if
    they can be allocated above the 32-bit address range. To limit the
    chances of having the first 4GB already full, objects will use
    DRM_MM_SEARCH_BELOW + DRM_MM_CREATE_TOP flags when possible.
    
    The libdrm user of the EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag is here:
    http://lists.freedesktop.org/archives/intel-gfx/2015-September/075836.html
    
    
    
    v2: Changed flag logic from neeeds_32b, to supports_48b.
    v3: Moved 48-bit support flag back to exec_object. (Chris, Daniel)
    v4: Split pin flags into PIN_ZONE_4G and PIN_HIGH; update PIN_OFFSET_MASK
    to use last PIN_ defined instead of hard-coded value; use correct limit
    check in eb_vma_misplaced. (Chris)
    v5: Don't touch PIN_OFFSET_MASK and update workaround comment (Chris)
    v6: Apply pin-high for ggtt too (Chris)
    v7: Handle simultaneous pin-high and pin-mappable end correctly (Akash)
        Fix check for entries currently using +4GB addresses, use min_t and
        other polish in object_bind_to_vm (Chris)
    v8: Commit message updated to point to libdrm patch.
    v9: vmas are allocated in the correct ozone, so only check flag when the
        vma has not been allocated. (Chris)
    
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v4)
    Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    101b506a