ufs: ufs-mediatek: Add UFSHCD_QUIRK_BROKEN_LSDBS_CAP for mt8195 SoC

The mt8195 controller doesn't have the LSD bit, first the controller is
compatible with UFSHCI version 2.1 and this bit is not part
of the specification. The MT8195 controller have a Multi Host Support
bit instead at bit(29).

Signed-off-by: Julien Massot <julien.massot@collabora.com>

drivers/ufs/host/ufs-mediatek.c

@@ -48,8 +48,21 @@ static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
 	{}
 };
 
+struct ufs_mtk_pdata {
+	unsigned int quirks;
+};
+
+/*
+ * mt8195 has 'Multi Host Support' (MHS) at bit 29 of the Host
+ * Controller Capabilities instead of the expected LSDB bit.
+ */
+struct ufs_mtk_pdata mt8195_pdata = {
+	.quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP,
+};
+
 static const struct of_device_id ufs_mtk_of_match[] = {
 	{ .compatible = "mediatek,mt8183-ufshci" },
+	{ .compatible = "mediatek,mt8195-ufshci", .data = &mt8195_pdata },
 	{},
 };
 MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
@@ -983,6 +996,7 @@ static int ufs_mtk_init(struct ufs_hba *hba)
 	struct device *dev = hba->dev;
 	struct ufs_mtk_host *host;
 	struct Scsi_Host *shost = hba->host;
+	const struct ufs_mtk_pdata *pdata = of_device_get_match_data(dev);
 	int err = 0;
 	struct arm_smccc_res res;
 
@@ -1037,6 +1051,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
 	/* Set runtime pm delay to replace default */
 	shost->rpm_autosuspend_delay = MTK_RPM_AUTOSUSPEND_DELAY_MS;
 
+	/* Apply platform specific quirks */
+	if (pdata)
+		hba->quirks |= pdata->quirks;
+
 	hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
 	hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_INTR;
 	hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_RTC;