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  1. Apr 30, 2018
  2. Apr 27, 2018
  3. Mar 23, 2018
  4. Mar 19, 2018
  5. Mar 14, 2018
  6. Feb 26, 2018
  7. Feb 14, 2018
  8. Feb 13, 2018
  9. Feb 12, 2018
    • Alexander Duyck's avatar
      i40e/i40evf: Add support for new mechanism of updating adaptive ITR · a0073a4b
      Alexander Duyck authored
      
      This patch replaces the existing mechanism for determining the correct
      value to program for adaptive ITR with yet another new and more
      complicated approach.
      
      The basic idea from a 30K foot view is that this new approach will push the
      Rx interrupt moderation up so that by default it starts in low latency and
      is gradually pushed up into a higher latency setup as long as doing so
      increases the number of packets processed, if the number of packets drops
      to 4 to 1 per packet we will reset and just base our ITR on the size of the
      packets being received. For Tx we leave it floating at a high interrupt
      delay and do not pull it down unless we start processing more than 112
      packets per interrupt. If we start exceeding that we will cut our interrupt
      rates in half until we are back below 112.
      
      The side effect of these patches are that we will be processing more
      packets per interrupt. This is both a good and a bad thing as it means we
      will not be blocking processing in the case of things like pktgen and XDP,
      but we will also be consuming a bit more CPU in the cases of things such as
      network throughput tests using netperf.
      
      One delta from this versus the ixgbe version of the changes is that I have
      made the interrupt moderation a bit more aggressive when we are in bulk
      mode by moving our "goldilocks zone" up from 48 to 96 to 56 to 112. The
      main motivation behind moving this is to address the fact that we need to
      update less frequently, and have more fine grained control due to the
      separate Tx and Rx ITR times.
      
      Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
      Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      a0073a4b
    • Alexander Duyck's avatar
      i40e/i40evf: Split container ITR into current_itr and target_itr · 556fdfd6
      Alexander Duyck authored
      
      This patch is mostly prep-work for replacing the current approach to
      programming the dynamic aka adaptive ITR. Specifically here what we are
      doing is splitting the Tx and Rx ITR each into two separate values.
      
      The first value current_itr represents the current value of the register.
      
      The second value target_itr represents the desired value of the register.
      
      The general plan by doing this is to allow for deferring the update of the
      ITR value under certain circumstances. For now we will work with what we
      have, but in the future I hope to change the behavior so that we always
      only update one ITR at a time using some simple logic to determine which
      ITR requires an update.
      
      Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
      Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      556fdfd6
    • Alexander Duyck's avatar
      i40e/i40evf: Clean-up of bits related to using q_vector->reg_idx · 8b99b117
      Alexander Duyck authored
      
      This patch is a further clean-up related to the change over to using
      q_vector->reg_idx when accessing the ITR registers. Specifically the code
      appears to have several other spots where we were computing the register
      offset manually and this resulted in errors in a few spots.
      
      Specifically in the i40evf functions for mapping queues to vectors it
      appears we may have had an off by 1 error since (v_idx - 1) for the first
      q_vector with an index of 0 would result in us returning -1 if I am not
      mistaken.
      
      Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
      Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      8b99b117
    • Alexander Duyck's avatar
      i40e/i40evf: Only track one ITR setting per ring instead of Tx/Rx · 40588ca6
      Alexander Duyck authored
      
      The rings are already split out into Tx and Rx rings so it doesn't make
      sense to have any single ring store both a Tx and Rx itr_setting value.
      Since that is the case drop the pair in favor of storing just a single ITR
      value.
      
      Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
      Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      40588ca6
  10. Jan 26, 2018
  11. Jan 23, 2018
  12. Jan 10, 2018
  13. Nov 22, 2017
    • Alan Brady's avatar
      i40evf: fix client notify of l2 params · 01acc73f
      Alan Brady authored
      
      The current method for notifying clients of l2 parameters is broken
      because we fail to copy the new parameters to the client instance
      struct, we need to do the notification before the client 'open' function
      pointer gets called, and lastly we should set the l2 parameters when
      first adding a client instance.
      
      This patch first introduces the i40evf_client_get_params function to
      prevent code duplication in the i40evf_client_add_instance and the
      i40evf_notify_client_l2_params functions.  We then fix the notify l2
      params function to actually copy the parameters to client instance
      struct and do the same in the *_add_instance' function.  Lastly this
      patch reorganizes the priority in which client tasks fire so that if the
      flag for notifying l2 params is set, it will trigger before the open
      because the client needs these new parameters as part of a client open
      task.
      
      Signed-off-by: default avatarAlan Brady <alan.brady@intel.com>
      Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      01acc73f
  14. Oct 18, 2017
  15. Oct 09, 2017
    • Jacob Keller's avatar
      i40e/i40evf: fix incorrect default ITR values on driver load · 42702559
      Jacob Keller authored
      
      The ITR register expects to be programmed in units of 2 microseconds.
      Because of this, all of the drivers I40E_ITR_* constants are in terms of
      this 2 microsecond register.
      
      Unfortunately, the rx_itr_default value is expected to be programmed in
      microseconds.
      
      Effectively the driver defaults to an ITR value of half the expected
      value (in terms of minimum microseconds between interrupts).
      
      Fix this by changing the default values to be calculated using
      ITR_REG_TO_USEC macro which indicates that we're converting from the
      register units into microseconds.
      
      Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
      Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      42702559
    • Alan Brady's avatar
      i40evf: fix mac filter removal timing issue · c766b9af
      Alan Brady authored
      
      Due to the asynchronous nature in which mac filters are added and
      deleted, there exists a bug in which filters are erroneously removed if
      removed then added again quickly.
      
      The events are as such:
          - filter marked for removal
          - same filter is re-added before watchdog that cleans up filters
          - we skip re-adding the filter because we have it already in the
      list
          - watchdog filter cleanup kicks off and filter is removed
      
      So when we were re-adding the same filter, it didn't actually get added
      because it already existed in the list, but was marked for removal and
      had yet to actually be removed.
      
      This patch fixes the issue by making sure that when adding a filter, if
      we find it already existing in our list, make sure it is not marked to
      be removed.
      
      Signed-off-by: default avatarAlan Brady <alan.brady@intel.com>
      Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      c766b9af
  16. Oct 06, 2017
    • Jacob Keller's avatar
      i40evf: enable support for VF VLAN tag stripping control · 0a3b4f70
      Jacob Keller authored
      
      A recent commit 809481484e5d ("i40e/i40evf: support for VF VLAN tag
      stripping control") added support for VFs to negotiate the control of
      VLAN tag stripping. This should have allowed VFs to disable the feature.
      Unfortunately, the flag was set only in netdev->feature flags and not in
      netdev->hw_features.
      
      This ultimately causes the stack to assume that it cannot change the
      flag, so it was unchangeable and marked as [fixed] in the ethtool -k
      output.
      
      Fix this by setting the feature in hw_features first, just as we do for
      the PF code. This enables ethtool -K to disable the feature correctly,
      and fully enables user control of the VLAN tag stripping feature.
      
      Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
      Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      0a3b4f70
    • Jacob Keller's avatar
      i40e/i40evf: spread CPU affinity hints across online CPUs only · be664cbe
      Jacob Keller authored
      
      Currently, when setting up the IRQ for a q_vector, we set an affinity
      hint based on the v_idx of that q_vector. Meaning a loop iterates on
      v_idx, which is an incremental value, and the cpumask is created based
      on this value.
      
      This is a problem in systems with multiple logical CPUs per core (like in
      simultaneous multithreading (SMT) scenarios). If we disable some logical
      CPUs, by turning SMT off for example, we will end up with a sparse
      cpu_online_mask, i.e., only the first CPU in a core is online, and
      incremental filling in q_vector cpumask might lead to multiple offline
      CPUs being assigned to q_vectors.
      
      Example: if we have a system with 8 cores each one containing 8 logical
      CPUs (SMT == 8 in this case), we have 64 CPUs in total. But if SMT is
      disabled, only the 1st CPU in each core remains online, so the
      cpu_online_mask in this case would have only 8 bits set, in a sparse way.
      
      In general case, when SMT is off the cpu_online_mask has only C bits set:
      0, 1*N, 2*N, ..., C*(N-1)  where
      C == # of cores;
      N == # of logical CPUs per core.
      In our example, only bits 0, 8, 16, 24, 32, 40, 48, 56 would be set.
      
      Instead, we should only assign hints for CPUs which are online. Even
      better, the kernel already provides a function, cpumask_local_spread()
      which takes an index and returns a CPU, spreading the interrupts across
      local NUMA nodes first, and then remote ones if necessary.
      
      Since we generally have a 1:1 mapping between vectors and CPUs, there
      is no real advantage to spreading vectors to local CPUs first. In order
      to avoid mismatch of the default XPS hints, we'll pass -1 so that it
      spreads across all CPUs without regard to the node locality.
      
      Note that we don't need to change the q_vector->affinity_mask as this is
      initialized to cpu_possible_mask, until an actual affinity is set and
      then notified back to us.
      
      Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
      Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      be664cbe
  17. Oct 02, 2017
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