AngeloGioacchino Del Regno authored 3 years ago and Nícolas F. R. A. Prado committed 3 years ago

In commit d687e056 ("soc: mediatek: mmsys: Add mt8192 mmsys routing table"),
the mmsys routing table for mt8192 was introduced but the input selector
for DITHER->DSI0 has no value assigned to it.

This means that we are clearing bit 0 instead of setting it, blocking
communication between these two blocks; due to that, any display that
is connected to DSI0 will not work, as no data will go through.
The effect of that issue is that, during bootup, the DRM will block for
some time, while atomically waiting for a vblank that never happens;
later, the situation doesn't get better, leaving the display in a
non-functional state.

To fix this issue, fix the route entry in the table by assigning the
dither input selector to MT8192_DISP_DSI0_SEL_IN.

Fixes: d687e056 ("soc: mediatek: mmsys: Add mt8192 mmsys routing table")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

MFG0 power domain requires an extra power supply on mt8192.

BUG=b:178776793
TEST=boot asurada and check display

[Similar patch is being upstreamed for 8183, we can wait for that
to land upstream, then upstream this as well]

Change-Id: I01f46bed82d927ea5871a15dc47e4d9093354f30
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2699573


Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>

The HW should be the same as mt8183 anyway so use its compatible so aal
probes and the drm driver can finish probing.

However with the current HACK to ignore DPI, this is not relevant.

With this the kernel is able to load the rootfs from the USB stick and
reach the shell.

Weiyi Lu authored 4 years ago and Nícolas F. R. A. Prado committed 3 years ago

Add power domains controller node for SoC mt8192

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
(am from https://patchwork.kernel.org/patch/11986729/)
(also found at https://lore.kernel.org/r/1608645594-18809-1-git-send-email-weiyi.lu@mediatek.com

)

BUG=b:153618847
TEST=Boot asurada

Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Change-Id: I62d044264cb1b108155a2ac5d3a39f07d040e969
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2605177


Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>

With this I'm able to read the serial from asurada.

These clocks are required for the platform bringup, in particular for
the display power domain.

Nicolas Dufresne authored 3 years ago and Daniel Almeida committed 3 years ago

These are signed values and will otherwise fail the validation in
v4l2-ctrls-core.c.

Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>

This was disabled because on upstream there was no support for this
feature.

Now that the support is in, enable it again.

In order to reduce decoder latency, enable H264 inner racing mode.

Send lat trans buffer information to core when trigger lat to work,
need not to wait until lat decode done.

Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>

Init some of VP9 frame decode params to default value.

Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>