incorrectly generating start/stop conditions on the bus.
Patch by Andrew Dyer, 26 Jul 2005

should look at LSB of L1CSRn registers to determine if L1 cache is
enabled, not the MSB.
Patch by Murray Jensen, 19 Jul 2005

Patch by Murray Jensen, 15 Jul 2005

Patch by Yuli Barcohen, 13 Jul 2005

ethernet and iic adapter code.
Patch by Michael Libeskind, 12 Jul 2005

Patch by Murray Jensen, 08 Jul 2005

Patch by Murray Jensen, 08 Jul 2005

Patch by Murray Jensen, 08 Jul 2005

Ignores the vendor TFTP server name option (#66).
Patch by Murray Jensen, 30 Jun 2005

Patch by Andy Fleming, 14 Jun 2005

Patch by Gerhard Jaeger, 21 Jun 2005

Patch by Sam Song, 19 Jun 2005

Patch by Sam Song, 19 Jun 2005

Patch by Sam Song, 19 Jun 2005

Patch by KokHow Teh, 16 Jun 2005

Patch by Rick Bronson, 15 Jun 2005

Patch by Andrew Dyer, 13 Jun 2005

- add support for Analog Devices Blackfin BF533 CPU
- add support for the ADI BF533 Stamp uClinux board
- add support for the ADI BF533 EZKit board
Patches by Richard Klingler, June 11th 2005:

Patch by Steven Scholz, 10 Jun 2005

variable to set clock
Patch by Yuli Barcohen, 05 Jun 2005

- Use correct flash sector size
- Use correct memory test end address
- Add support for bzip2 compression
- Various small fixes
Patch by Yuli Barcohen, 05 Jun 2005

- Fix SDRAM timing on both local bus and 60x bus
- Add support for second flash bank (SIMM)
- Change boot flash base
Patch by Yuli Barcohen, 05 Jun 2005

add support for second FEC on Adder87x board.
Patch by Yuli Barcohen, 05 Jun 2005

Patch by Greg Ungerer, 04 Jun 2005

Patch by Friedrich Lobenstock, 02 Jun 2005

Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005

Patch by Greg Ungerer, 21 May 2005

Patch by Jean-Paul Saman, 01 Mar 2005

Patch by Robin Gilks, 23 Dec 2004

Remove build results from repository

(This is Work in Progress!)

Patch by Stefan Roese, 4 Mar 2006

Patch by Markus Klotzbuecher, 27 Feb 2006

Patch by Stefan Roese, 1 Mar 2006